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AR# 65542

2015.3/2015.4 Vivado Synthesis - Unable to select the Use VHDL 2008 option when the Target Language is Verilog


When the "set_param porject.enableVHDL2008 1" Tcl switch is turned on, a "Use VHDL 2008" switch will appear in the General Settings window.

If the Target Language is set to Verilog, this option will be grayed out.


To work around this issue, change the Target Language to VHDL.

Starting with Vivado 2016.1, the project.enableVHDL2008 switch is turned on by default. You will not see "Use VHDL 2008" switch in the General Settings window, but VHDL 2008 is supported by default.

AR# 65542
Date 04/13/2016
Status Active
Type Known Issues
  • FPGA Device Families
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2015.4.1
  • Vivado Design Suite - 2015.4.2
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