AR# 65545

Zynq-7000 SoC, APU - Under very rare timing circumstances, data corruption might occur on a dirty cache line that is evicted from the L1 Data Cache due to another cache line being entirely written

Description

Under very rare timing circumstances, data corruption might occur on a dirty cache line that is evicted from the L1 Data Cache due to another cache line being entirely written.

Solution


Impact:
Minor. The erratum might lead to data corruption.
Work-around:

This erratum can be worked around by setting bit[22] of the undocumented Diagnostic Control Register to 1. This register is encoded as CP15 c15 0 c0 1.
The bit can be written in Secure state only, with the following Read/Modify/Write code sequence:

MRC p15,0,rt,c15,c0,1
ORR rt,rt,#0x00400000
MCR p15,0,rt,c15,c0,1

When this bit is set, the processor is unable to switch into Read-Allocate (streaming) mode, which means that this erratum cannot occur.
Setting this bit could possibly result in a visible drop in performance for routines that perform intensive memory accesses, such as memset() or memcpy().
However, the work-around is not expected to create any significant performance degradation in most standard applications.

Configurations Affected:
This erratum affects configurations with either:

- One processor if the ACP is present
- Two or more processors

Device Revision(s) Affected:All. No plan to fix.
Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences 
Third Party Errata:Arm Errata #845369

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 SoC Devices - Silicon Revision Differences N/A N/A
AR# 65545
Date 05/28/2018
Status Active
Type Design Advisory
Devices