I am attempting to launch simulation, but it fails with an error similar to the following:
Starting static elaboration
ERROR: [VRFC 10-451] cannot open file 'int_infile' [/eda/my_proj/my_proj.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/7b054ed9/simulation/blk_mem_gen_v8_2.vhd:2832] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-99] Step results log file:'/eda/my_proj/my_proj .sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/eda/my_proj/my_proj .sim/sim_1/behav/elaborate.log' file for more information. launch_simulation: Time (s): cpu = 00:01:18 ; elapsed = 00:02:48 . Memory (MB): peak = 6086.723 ; gain = 5.004 ; free physical = 15550 ; free virtual = 73416
It appears that the .mem file is not getting copied correctly to the sim directory for the simulation run.
This issue is scheduled to be fixed in Vivado 2016.1.
The current work-around is to regenerate output products for all IP and BD in the design using the "global" setting.
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