Description

Solution

(c) Copyright 2015 Xilinx, Inc. All rights reserved.

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100G Ethernet (1.7)

*Version 1.7

*RS-FEC integration in between CMAC and GT

*1588 Transparent Clock 1-step, 2-step and Both

*Updated the port names for the reset ports

*Kintex095 device support added

*Support for RX buffer bypass for CAUI10 GTY and runtime switchable case

*Reduced the pipeline stages to 2-stage in between CMAC and GTH for xcvu440 device

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

10G Ethernet MAC (15.0)

*Version 15.0 (Rev. 2)

*Fixed Link Fault not asserted after 4 consecutive fault code groups.

*Fixed bug in TX Legacy PAUSE logic in which the pause frame is not transmitted if there have been no previous Data frames

*Changed configuration logic to force DIC enable low if IFG Extend is enabled

*Fixed RX statistics vector for very short frames with stacked VLAN header fields

*UltraScale Plus device support is limited to simulation only. Timing violations may bee seen when implementing the IP on UltraScale Plus devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

*Version 6.0 (Rev. 2)

*Support for UltraScale plus devices; the device support is limited to functional simulation only. Implementation and post implementation simulations might not be successful for certain devices.

*Added support for xcku095 device family

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

10G Ethernet Subsystem (3.0)

*Version 3.0 (Rev. 2)

*No Functional changes.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*To bring out TXOUTCLKSEL and reset control for holding PCS reset so users can enable PRBS test in the core (as per AR 63704).

*Support for UltraScale plus devices; the device support is limited to functional simulation only. Implementation and post implementation simulations might not be successful for certain devices.

*Revision change in one or more subcores

10G/25G Ethernet Subsystem (1.0)

*Version 1.0

*MAC and PCS support for 10G and 25G

*Base-KR and Base-R support

*AN/LT support

1G/2.5G Ethernet PCS/PMA or SGMII (15.1)

*Version 15.1

*Added Zynq UltraScale plus support.

*Changing txdiffctrl default value to "1000".

*Added 2.5G support to Artix-7 devices (-2 and -3 speed grades) devices.

*Added 3ms startup delay on CPLL/PLL0 controlled by EXAMPLE_SIMULATION.

*GT wizard updated to v3_6 for Series-7 transceivers.

*Register 2 and Register 3 updated with OUI values for Xilinx.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

32-bit Initiator/Target for PCI (7-Series) (5.0)

*Version 5.0 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

3GPP LTE Channel Estimator (2.0)

*Version 2.0 (Rev. 9)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

3GPP LTE MIMO Decoder (3.0)

*Version 3.0 (Rev. 9)

*Added utility subcore dependency to simplify new device support

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

3GPP LTE MIMO Encoder (4.0)

*Version 4.0 (Rev. 8)

*Added utility subcore dependency to simplify new device support

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

3GPP Mixed Mode Turbo Decoder (2.0)

*Version 2.0 (Rev. 9)

*HDL files touched to overcome namespace clash with new VHDL-2008 libraries. No change to functionality

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

3GPP Turbo Encoder (5.0)

*Version 5.0 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

3GPPLTE Turbo Encoder (4.0)

*Version 4.0 (Rev. 8)

*Added utility subcore dependency to simplify new device support

*HDL files touched to overcome namespace clash with new VHDL-2008 libraries. No change to functionality

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

64-bit Initiator/Target for PCI (7-Series) (5.0)

*Version 5.0 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

7 Series FPGAs Transceivers Wizard (3.6)

*Version 3.6

*Added support for XC7Z030SBV485 devices

*Added GUI option to extend CPLL or QPLL reset by 3 ms

*Added HDMI template support for GTX and GTP based devices

*Renamed vby1 template to vby1_no_SSC

*Added PRBS patterns for raw encoding for GTZ

7 Series Integrated Block for PCI Express (3.2)

*Version 3.2

*For EXTERNAL PIPE INTERFACE mode, a new file xil_sig2pipe.v is delivered in the simulation directory and it replaces the phy_sig_gen.v. BFM/VIPs should interface with the xil_sig2pipe instance in board.v

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AHB-Lite to AXI Bridge (3.0)

*Version 3.0 (Rev. 4)

*Added up to 64 bit address width support for on AHBLite and AXI interfaces

*Fixed RTL for early burst termination issue (applicable when there are back to back single beat transactions in pipeline)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI 1G/2.5G Ethernet Subsystem (7.0)

*Version 7.0 (Rev. 2)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Support for UltraScale plus devices; the device support is limited to functional simulation only. Implementation and post implementation simulations might not be successful for certain devices.

*Revision change in one or more subcores

AXI AHBLite Bridge (3.0)

*Version 3.0 (Rev. 4)

*Added up to 64 bit address width support for on AHBLite and AXI interfaces

*Example design update w.r.t. helper core calls

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI APB Bridge (3.0)

*Version 3.0 (Rev. 4)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI BFM Cores (5.0)

*Version 5.0 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI BRAM Controller (4.0)

*Version 4.0 (Rev. 5)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Address range supported is increased to 2G in IP Integrator

AXI Bridge for PCI Express Gen3 Subsystem (2.0)

*Version 2.0

*Added support for Shared logic

*Added support for Rootport configuration

*Added support for sfva784 package for xcku035 and xcku040

*Added support for xcku025, xcku085 and xcku095 devices

*Added option for selecting number of outstanding AXI Master/Slave Write/Read requests

*For EXTERNAL PIPE INTERFACE mode, a new file xil_sig2pipe.v is delivered in the simulation directory and it replaces the phy_sig_gen.v. BFM/VIPs should interface with the xil_sig2pipe instance in board.v

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI CAN (5.0)

*Version 5.0 (Rev. 9)

*Fixed an issue in handling back to back transactions at core AXI Lite interface (AR 63102).

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Central Direct Memory Access (4.1)

*Version 4.1 (Rev. 6)

*Mark Debug attribute removed from core HDL

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Chip2Chip Bridge (4.2)

*Version 4.2 (Rev. 6)

*Added up to 64-bit address width support for AXI4 master interface

*Helper core version update (fifo_generator_v13_0)

*IP core XDC updated as per helper core FIFO XDC update

*Example design updated to use Aurora_64b66b_v11_0

*Enabled example design support for aurora configuration with UltraScale plus devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI Clock Converter (2.1)

*Version 2.1 (Rev. 5)

*Update to fifo_generator 13.0

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI Crossbar (2.1)

*Version 2.1 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Data FIFO (2.1)

*Version 2.1 (Rev. 5)

*Updated to use FIFO Generator v13.0

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI Data Width Converter (2.1)

*Version 2.1 (Rev. 6)

*Updated to use blk_mem_gen v8.3 and fifo_generator v13.0

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI DataMover (5.1)

*Version 5.1 (Rev. 8)

*IP core XDC updated as per helper core FIFO XDC update

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Direct Memory Access (7.1)

*Version 7.1 (Rev. 7)

*Increased AXI4 outstanding request depth from 1 to 4

*Minor RTL change to fix CDC warning

*IP core XDC updated as per helper core FIFO XDC update

*Mark Debug attribute removed from core HDL

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI EMC (3.0)

*Version 3.0 (Rev. 6)

*Added IOB attribute to interface flops (through core HDL and through XDC constraints where applicable)

*Added option to include STARTUPE3 primitive inside the core

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI EPC (2.0)

*Version 2.0 (Rev. 9)

*Example design update w.r.t. helper core calls

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Ethernet Buffer (2.0)

*Version 2.0 (Rev. 9)

*Updates to support 1588 mode inband control and time stamp.

*Support phy_reset generation based on AXI lite clock.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Ethernet Clocking (2.0)

*Version 2.0 (Rev. 2)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI EthernetLite (3.0)

*Version 3.0 (Rev. 4)

*IP core XDC updated as per helper core FIFO XDC update

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI GPIO (2.0)

*Version 2.0 (Rev. 8)

*IP update to support latest board flow, no functional or interface changes

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI HWICAP (3.0)

*Version 3.0 (Rev. 10)

*Added option to make ICAP primitive external to the core

*Added interface to access external ICAP primitive

*Added option to share unused ports of STARTUPE2 primitive

*Mark Debug attribute removed from core hdl

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI IIC (2.0)

*Version 2.0 (Rev. 9)

*Example design update w.r.t. helper core calls

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Interconnect (2.1)

*Version 2.1 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Interrupt Controller (4.1)

*Version 4.1 (Rev. 5)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*Improved automatic setting of interrupt controller IVAR reset value from connected processor

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Lite IPIF (3.0)

*Version 3.0 (Rev. 3)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI MMU (2.1)

*Version 2.1 (Rev. 4)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Master Burst (2.0)

*Version 2.0 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Memory Mapped To PCI Express (2.7)

*Version 2.7

*Fixed GTP DRP write issue - (Xilinx Answer AR63182)

*For EXTERNAL PIPE INTERFACE mode, a new file xil_sig2pipe.v is delivered in the simulation directory and it replaces the phy_sig_gen.v. BFM/VIPs should interface with the xil_sig2pipe instance in board.v

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Memory Mapped to Stream Mapper (1.1)

*Version 1.1 (Rev. 5)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Performance Monitor (5.0)

*Version 5.0 (Rev. 8)

*Added up to 64-bit address width support for AXI4 master interface

*Example design minor updates. No functional changes

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI Protocol Checker (1.1)

*Version 1.1 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI Protocol Converter (2.1)

*Version 2.1 (Rev. 6)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Quad SPI (3.2)

*Version 3.2 (Rev. 5)

*Fixed extra toggles on SCK clock line (AR 65224)

*Fixed receive bit shift issue in Standard Master Mode (AR 65225)

*Added option to include STARTUPE3 primitive inside the core

*Added option to share unused ports of STARTUPE2 primitive

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Register Slice (2.1)

*Version 2.1 (Rev. 6)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI TFT Controller (2.0)

*Version 2.0 (Rev. 10)

*Added up to 64-bit address width support for AXI4 master interface

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Timebase Watchdog Timer (2.0)

*Version 2.0 (Rev. 8)

*Example design update w.r.t. helper core calls

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Timer (2.0)

*Version 2.0 (Rev. 8)

*Example design update w.r.t. helper core calls

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Traffic Generator (2.0)

*Version 2.0 (Rev. 7)

*Added up to 64 bit address width support for AXI4 master interface

*Updated IP to support 24 bit TLEN in streaming mode

*Updated IP to support up to 32 bit User Width for AXI slave interface

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI UART16550 (2.0)

*Version 2.0 (Rev. 8)

*Enhanced IP to Support xilinx future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI USB2 Device (5.0)

*Version 5.0 (Rev. 7)

*Added up to 64 bit address width support for AXI4 master interface

*Core RTL updated to fix CDC warnings

*Helper core version update (fifo_generator_v13_0)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Uartlite (2.0)

*Version 2.0 (Rev. 10)

*Minor updates to example design. No functional changes.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Video Direct Memory Access (6.2)

*Version 6.2 (Rev. 5)

*Helper core version update (fifo_generator_v13_0)

*IP core XDC updated as per helper core FIFO XDC update

*Example Design Updated to fix CDC warning and async FIFO clocking recommendation

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI Virtual FIFO Controller (2.0)

*Version 2.0 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI-Stream FIFO (4.1)

*Version 4.1 (Rev. 3)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI4-Stream Accelerator Adapter (2.1)

*Version 2.1 (Rev. 5)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI4-Stream Broadcaster (1.1)

*Version 1.1 (Rev. 6)

*Repackaged IP to improve internal automation.  No functional changes.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI4-Stream Clock Converter (1.1)

*Version 1.1 (Rev. 7)

*Updated XDC in sync with fifo changes

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI4-Stream Combiner (1.1)

*Version 1.1 (Rev. 5)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI4-Stream Data FIFO (1.1)

*Version 1.1 (Rev. 7)

*Repackaged to improve internal automation.  No functional change.

*Updated XDC in sync with FIFO changes

*Updated to use FIFO Generator v13.0

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI4-Stream Data Width Converter (1.1)

*Version 1.1 (Rev. 5)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Configurations where there is non-multiple tdata width conversion (e.g., 2:3, 4:3, etc), no TKEEP and  no TID, TDEST or TLAST signals present were found to be adding the TKEEP signal with all bits tied to LOW to the output M_AXIS interface.  The TKEEP output can be ignored in this configuration. While the TKEEP is not needed, it has been kept to not break backwards compatibility and the vector is now being driven HIGH to produce a valid output.  Configurations that require an upsizer (more than 1 input transfer is accumulated into 1 or more output transfers) and have TID/TDEST/TLAST and no TKEEP, will still produce a TKEEP.  The TKEEP in this instance is not always tied HIGH and must be monitored if the input stream is not conditioned to ensure that TID/TDEST/TLAST do not toggle during accumulation.

*Revision change in one or more subcores

AXI4-Stream Interconnect (2.1)

*Version 2.1 (Rev. 7)

*Update IP integrator automation to improve address map handling of routing mode register interface.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Update IP Configurator to omit BASE/HIGH TDEST pairs when using control register routing.

*Revision change in one or more subcores

AXI4-Stream Protocol Checker (1.1)

*Version 1.1 (Rev. 6)

*Repackaged to improve internal automation. No functional changes.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI4-Stream Register Slice (1.1)

*Version 1.1 (Rev. 6)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

AXI4-Stream Subset Converter (1.1)

*Version 1.1 (Rev. 6)

*Added support for remapping most stream signals from a combination of other stream signals and constants

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI4-Stream Switch (1.1)

*Version 1.1 (Rev. 6)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

AXI4-Stream to Video Out (4.0)

*Version 4.0

*Major revision of core to v4.0

*Optimized architecture for speed

*Replaced internal FIFO with FIFO generator IP

*Added user parameter for component width conversion

*Added user parameter option for synchronous or asynchronous clock mode

*Added overflow, underflow, and status ports

*Changed default timing mode to slave

*Added support for Zynq and Kintex UltraScale+ devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Accumulator (12.0)

*Version 12.0 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Adder/Subtracter (12.0)

*Version 12.0 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Aurora 64B66B (11.0)

*Version 11.0

*Added support for GTY up to 25Gbps line rates

*One GTREFCLK input per quad is a requirement for line rates above 16.375Gbps for GTY

*CRC implementation is not backward compatible for line rates above 16.375Gbps for GTY

*UFC and USERK interfaces are not supported for line rates above 16.375Gbps for GTY

*Added support for XC7Z030SBV485 and XC7Z030ISBV485 devices

*UltraScale GT Wizard and FIFO subcore versions updated

*s_axi_user_k_tx_tready output gated with channel_up

*TXMASTERCHANNEL and RXMASTERCHANNEL selection updated for UltraScale Transceivers

*Added support for UltraScale+ devices

Aurora 8B10B (11.0)

*Version 11.0 (Rev. 2)

*Updated RTL to fix CDC warnings

*Added support for UltraScale+ devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Binary Counter (12.0)

*Version 12.0 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Block Memory Generator (8.3)

*Version 8.3

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption

*Simulation models are delivered in VHDL only

CIC Compiler (4.0)

*Version 4.0 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

CORDIC (6.0)

*Version 6.0 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

CPRI (8.5)

*Version 8.5

*Updated to use version 1.6 of the UltraScale GT Wizard.

*Added transceiver selection for UltraScale devices to the GUI.

*Improved state machine sequencing for the 7-series GTs.

*Added support for UltraScale+.

*Added insertion loss setting to switch between LPM and DFE mode in UltraScale devices.

*Restart UltraScale RX buffer bypass state machine when transceiver PMARESETDONE is low.

*Restart UltraScale TX buffer bypass state machine when TX resetdone is low.

*Added reset_aux_clk port for instances that do not use the AXI control interface.

*Replace the SSD1 and SSD2 characters in the received Ethernet data with 0x55 in buffer bypass mode.

*Changed watchdog reset to only reset the receiver section of the transceiver.

*Assert the TXUSERRDY input of the transceiver only when the MMCM has locked in 7-Series.

*Improved DRP arbitration by moving arbiter adjacent to the transceiver.

*Added UltraScale and UltraScale+ support for new line rates 8.11008Gbps and 12.16512Gbps.

*CDC FIFO Fill level added to decrease the latency through the master core.

*Synchronized the TXPHINITDONE input to the TX alignment block onto the stable clock.

*Mu-Law compression example added to the example design.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Chroma Resampler (4.0)

*Version 4.0 (Rev. 7)

*Added support for Zynq and Kintex UltraScale+ devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Clocking Wizard (5.2)

*Version 5.2

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported

*Phase alignment feature is removed for UltraScale PLL as primitive has limited capabilities of supporting this feature

*When clocking wizard is targeted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format

*Example design and simulation files are delivered in Verilog only

Color Correction Matrix (6.0)

*Version 6.0 (Rev. 8)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Color Filter Array Interpolation (7.0)

*Version 7.0 (Rev. 7)

*Added support for Zynq and Kintex UltraScale+ devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Complex Multiplier (6.0)

*Version 6.0 (Rev. 9)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Convolution Encoder (9.0)

*Version 9.0 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

DDR3 SDRAM (MIG) (1.0)

*Version 1.0

*Initial release

*Derived from MIG IP in previous releases

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Resolved issue related to Dynamic DCI does not work for select ES devices.

*Resolved issue related to [Xicom 50-24] error message occurring after programming device.

*Resolved issue related to customization GUI showing incorrect Enable Chip Select Pin option when recustomizing IP.

DDR4 SDRAM (MIG) (1.0)

*Version 1.0

*Initial release

*Derived from MIG IP in previous releases

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Resolved issue related to Dynamic DCI does not work for select ES devices.

*Resolved issue related to CAS Latency setting of 17 resulting in calibration failures during DQS Gate Calibration.

*Resolved issue related to [Xicom 50-24] error message occurring after programming device.

*Resolved issue related to customization GUI showing incorrect Enable Chip Select Pin option when recustomizing IP.

DDS Compiler (6.0)

*Version 6.0 (Rev. 10)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*GUI PINC calculation when using System parameters in Rasterized Mode corrected

*Revision change in one or more subcores

DSP48 Macro (3.0)

*Version 3.0 (Rev. 10)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

DUC/DDC Compiler (3.0)

*Version 3.0 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Discrete Fourier Transform (4.0)

*Version 4.0 (Rev. 9)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Worked around LSB mismatch between C model and IP seen when simulating with Vivado Simulator or Cadence IES

*Revision change in one or more subcores

DisplayPort (6.1)

*Version 6.1

*Added External PHY support for subsystems

*Fixed RX equalization mode to LPM only

*Updated RX DRP configuration to support DP159 forwarded clock

*Added two new REFCLK ports in UltraScale RX to support forwarded clock for 2.7/5.4Ghz and external reference clock for 1.62Ghz

*Upgraded fifo_generator_v12_0 to fifo_generator_v13_0

*Added UltraScale+ device support

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Distributed Memory Generator (8.0)

*Version 8.0 (Rev. 9)

*Delivering only vhdl simulation model, Stopped delivery of Verilog simulation model.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Divider Generator (5.1)

*Version 5.1 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

ECC (2.0)

*Version 2.0 (Rev. 9)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Ethernet PHY MII to Reduced MII (2.0)

*Version 2.0 (Rev. 8)

*Example design update w.r.t. helper core calls

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

FIFO Generator (13.0)

*Version 13.0

*Asynchronous reset support is removed

*Added asymmetric port width support for 7-series Common Clock Block RAM FIFO

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

FIR Compiler (7.2)

*Version 7.2 (Rev. 4)

*Add constraints file to suppress expected memory collision warnings during post-synthesis simulation.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Correction to GUI reported latency estimate for polyphase interpolation configurations.

*Revision change in one or more subcores

Fast Fourier Transform (9.0)

*Version 9.0 (Rev. 8)

*Bugfix for incorrect output data in block floating point mode for Radix-2 architecture when resets are applied close together

*C model runtime performance improvement

*Reduced the number of warning messages seen during simulator elaboration

*Corrected HDL assertion logic in simulation-only checker which was missing a reset clause

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Bugfix for incorrect input range detection for Radix-2 Lite architecture using block floating point scaling

*Revision change in one or more subcores

Fixed Interval Timer (2.0)

*Version 2.0 (Rev. 6)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Floating-point (7.1)

*Version 7.1

*Added optimizations for half precision operators.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Removed IP GUI resource utilization graph tab now full performance and resource figures are available on xilinx.com.

*Added support for fixed-to-float conversions from uint32, uint64 and int64 formats.

*Added medium DSP48 usage option for single-precision Add/Subtract

*Revision change in one or more subcores

G.709 FEC Encoder/Decoder (2.2)

*Version 2.2 (Rev. 1)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Resets removed from datapath signals in OTN mode to alleviate congestion.

*OTU4 BROMSs converted to LUTROMs

*Revision change in one or more subcores

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

*Version 1.0 (Rev. 10)

*Corrected family support syntax, no change to supported devices, speed grades or parts

*Added utility subcore dependency to simplify new device support

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

*Version 2.0 (Rev. 10)

*Corrected family support syntax, no change to supported devices, speed grades or parts

*Added utility subcore dependency to simplify new device support

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Gamma Correction (7.0)

*Version 7.0 (Rev. 8)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Gmii to Rgmii (4.0)

*Version 4.0 (Rev. 1)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

High Speed SelectIO Wizard (2.0)

*Version 2.0

*Core is re-architected

*Enhanced configurability to support mix of pin directions (Tx, Rx, Bidir, Mix of all)

*Added user selectable receive clock/strobe to data relationship

*Extended FIFO write clock availability to fabric logic

*Added user selectable PLL input clock options based on the line speed

*Enhanced pin planning with exhaustive design rule check to ensure 'correct by construction' wizard

*Comprehensive reset sequence to improve reliability

*Enhanced the data speed support up to 1300 Mbps for serialization factor 4

*Added UltraScale+ device support

*High Speed SelectIO Wizard v1.1 offered multiple bitslip choices. Bitslip option is restricted to BITS_PER_SLIP only in High Speed SelectIO Wizard v2.0

IBERT 7 Series GTH (3.0)

*Version 3.0 (Rev. 10)

*Updated some procs for REFCLK selection update.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

IBERT 7 Series GTP (3.0)

*Version 3.0 (Rev. 9)

*Updated max line rate for Zynq device.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

IBERT 7 Series GTX (3.0)

*Version 3.0 (Rev. 10)

*Updated some procs for REFCLK selection update.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

IBERT 7 Series GTZ (3.1)

*Version 3.1 (Rev. 8)

*Cleaned up supporting tcl files

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

IBERT UltraScale GTH (1.3)

*Version 1.3

*Changed the default value to bitstring of parameters whose value format is bitstring and value was hex.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Added optional port txoutclk_o. This port is enabled only when user selects option Add_RXOUTCLK Probes

*Revision change in one or more subcores

IBERT UltraScale GTY (1.2)

*Version 1.2

*Changed the default value to bitstring of parameters whose value format is bitstring and value was hex.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Added optional port txoutclk_o. This port is enabled only when user selects option Add_RXOUTCLK Probes

*Revision change in one or more subcores

IEEE 802.3bj RS-FEC (1.0)

*Version 1.0 (Rev. 2)

*Up versioned the GT wizard in the example design

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

ILA (Integrated Logic Analyzer) (6.0)

*Version 6.0

*Fixed Timing10 DRC violations in ILA IP.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

IOModule (3.0)

*Version 3.0 (Rev. 3)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*Updated C_MASK and C_IO_MASK calculation to take into account if the connected processor is a lockstep slave

*Improved automatic setting of interrupt controller base vector from connected processor

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Image Enhancement (8.0)

*Version 8.0 (Rev. 8)

*Added support for Zynq and Kintex UltraScale+ devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Interlaken (1.7)

*Version 1.7

*AXI4-Lite support added for control and status

*GTWIZ version is updated to 1_6

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Updated the port names for the reset ports

*CLKWIZ version is updated to 5_2

*Added support for UltraScale Plus devices

*Kintex095 device new parts support added

*OOBFC feature enabled back

Interleaver/De-interleaver (8.0)

*Version 8.0 (Rev. 7)

*Updated file handling functions in HDL to operate correctly with Vivado Synthesis 2015.3.  No behavioral changes.

*HDL files touched to overcome namespace clash with new VHDL-2008 libraries. No change to functionality

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

JESD204 (6.2)

*Version 6.2

*Added Support for UltraScale GTY Transceiver

*Improved detection of Code Group Sync across multiple lanes

*Improved detection of transition from Alignment characters to ILA data

*Changed default values of gt_txpd and gt_rxpd when shared logic is included in the core and transceiver debug is disabled. See PG066 for more information

*Improved AXI Write duration by decreasing write cycle

*Improved reliability of gt_reset outputs

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*A BUFG which was being driven by the DRPCLK input in the clocking module has been removed

JESD204 PHY (3.0)

*Version 3.0

*Fixed CPLLPD connection. Output from AXI register map was not connected to the input of the Transceiver for UltraScale devices when AXI4-Lite enabled

*Added two new ports, tx_sys_reset and rx_sys_reset. See PG198 for details

*Added new resets to AXI register space, tx_sys_reset_axi and rx_sys_reset_axi

*Removed unused TX and RX clock select registers for each individual lane from AXI register space. See PG198 for more information

*Functionality of tx_reset_gt and rx_reset_gt has changed to reset only the transceiver channel (gttxreset and gtrxreset inputs of Transceiver). These reset no longer reset the PLLs. See PG198 for more information

*Optimized the Common and Transceiver selectors as a single register for each in the configuration sub-bank. Previously individual registers in the sub-banks. See PG198 for more information

*Added mmcm_locked output port to 7-Series Artix configurations with Shared Logic in Core enabled

*Added support for UltraScale GTY Transceivers

*Added GUI option to select transceiver channel placement. UltraScale configurations only

*Added GUI option to extend reset by 3ms for fast programming modes such as BPI or PCAP. 7-Series only

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

JTAG to AXI Master (1.1)

*Version 1.1

*64-Bit address support

*Added internal register for data width and id width

*uplus device support

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Updated FIFO generator from v12.0 to v13.0

*Revision change in one or more subcores

LMB BRAM Controller (4.0)

*Version 4.0 (Rev. 7)

*Updated family names for additional UltraScale devices

*Enhanced detection of lockstep master when the connected processor is a lockstep slave

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

LTE DL Channel Encoder (3.0)

*Version 3.0 (Rev. 8)

*HDL files touched to overcome namespace clash with new VHDL-2008 libraries. No change to functionality

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

LTE Fast Fourier Transform (2.0)

*Version 2.0 (Rev. 9)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

LTE PUCCH Receiver (2.0)

*Version 2.0 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

LTE RACH Detector (2.0)

*Version 2.0 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

LTE UL Channel Decoder (4.0)

*Version 4.0 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Local Memory Bus (LMB) 1.0 (3.0)

*Version 3.0 (Rev. 7)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

MIPI CSI-2 Rx Controller (1.0)

*Version 1.0

*Initial release

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

MIPI CSI-2 Rx Subsystem (1.0)

*Version 1.0

*Initial release

*Subsystem with integrated DPHY and CSI-2 Rx Controller.

*Support for 1 to 4 DPHY lanes

*AXI4-Stream Video output interface

*Optional AXI IIC support for Camera Control Interface (CCI)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

MIPI D-PHY (1.0)

*Version 1.0

*Initial release

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Mailbox (2.1)

*Version 2.1 (Rev. 5)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Memory Helper Core (1.0)

*Version 1.0

*Initial Support. Helper Core for QDRIV, QDRIV PHY, QDRIIP, QDRIIP PHY, RLDRAM3, RLDRAM3 PHY, DDR3 SDRAM, DDR3 SDRAM PHY, DDR4 SDRAM, DDR4 SDRAM PHY IPs.

Memory Interface Generator (MIG 7 Series) (2.4)

*Version 2.4

*RLDRAM II and QDRII+ SRAM write calibration and complex read calibration enhancements.

*RLDRAM III complex read calibration enhancements.

MicroBlaze (9.5)

*Version 9.5 (Rev. 2)

*Updated family names for additional UltraScale devices

*Added LMB and AXI monitor interfaces to simplify lockstep slave bus interface connection

*Improved lockstep handling to hide slave processors from ELF file association

*Enhanced detection of lockstep master from a lockstep slave processor

*HASH(0x1c2b1d20)

*HASH(0x1c2b1d30)

*Reduced warnings in synthesis

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

MicroBlaze Debug Module (MDM) (3.2)

*Version 3.2 (Rev. 4)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*Improved performance for debug access to LMB

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

MicroBlaze MCS (2.3)

*Version 2.3 (Rev. 2)

*Updated family names for additional UltraScale devices

*Updated with latest subcore versions

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Multiplier (12.0)

*Version 12.0 (Rev. 9)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Multiply Adder (3.0)

*Version 3.0 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Mutex (2.1)

*Version 2.1 (Rev. 5)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

PCIe DMA Subsystem (1.0)

*Version 1.0

*Initial release

Partial Reconfiguration Controller (1.0)

*Version 1.0 (Rev. 1)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Updated the fifo_generator to v13.0.  There is no change to the PRC's functionality

*Changed the interface type on reset and icap_reset from undef to xilinx.com:signal:reset:1.0.  This fixes a bug where IPI designer assistance connects the core's active low reset to an active high reset.

*Changed the API to disallow negative bitstream sizes.

*Changed the GUI to make sure allocated triggers and allocated RM values are always accurately displayed in the GUI.

*Fixed  a bug where the trigger registers couldn't be read.

*Revision change in one or more subcores

Partial Reconfiguration Decoupler (1.0)

*Version 1.0

*Initial Release

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Peak Cancellation Crest Factor Reduction (6.0)

*Version 6.0 (Rev. 2)

*Fixes for DC bias as discussed in AR 64915

*Support for UltraScale plus devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Processor System Reset (5.0)

*Version 5.0 (Rev. 8)

*Renamed the internal module to avoid conflict with VHDL2008 keyword, no functional change.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

QDRII+ SRAM (MIG) (1.0)

*Version 1.0

*ATG support added

*XSDB parameters enhanced

*Few calibration related fixes

QSGMII (3.3)

*Version 3.3 (Rev. 2)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Changed version of helper core gig_ethernet_pcs_pma from v15_0 to v15_1

*Added support for xcku095 device family

RAM-based Shift Register (12.0)

*Version 12.0 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Updated COE-to-MIF code to support IP Core Container flow

*Revision change in one or more subcores

RGB to YCrCb Color-Space Converter (7.1)

*Version 7.1 (Rev. 6)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

RLDRAM3 (MIG) (1.0)

*Version 1.0

*Extended Read Latency support

*Address mux support

*Updated XSDB status and error messaging

RXAUI (4.3)

*Version 4.3 (Rev. 2)

*Updated to use the latest GT UltraScale Wizard v1.6

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Added support for UltraScale plus devices

*Added support for xcku095 device family

*Revision change in one or more subcores

Reed-Solomon Decoder (9.0)

*Version 9.0 (Rev. 9)

*Many signals given explicit initial values to suppress warnings in simulation regarding X in arithmetic operation.

*HDL files touched to overcome namespace clash with new VHDL-2008 libraries. No change to functionality

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Updated COE-to-MIF code to support IP Core Container flow

*Initialization added to signal in syndrome to overcome VCS issue.

*Revision change in one or more subcores

Reed-Solomon Encoder (9.0)

*Version 9.0 (Rev. 8)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

S/PDIF (2.0)

*Version 2.0 (Rev. 9)

*Example design update

*Constraints updated for FIFO changes

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

SMPTE 2022-1/2 Video over IP Receiver (2.0)

*Version 2.0 (Rev. 3)

*Added support for Zynq UltraScale+ MPSoC, Kintex UltraScale+ and Virtex UltraScale+

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

SMPTE 2022-1/2 Video over IP Transmitter (2.0)

*Version 2.0 (Rev. 3)

*Added support for Zynq UltraScale+ MPSoC, Kintex UltraScale+ and Virtex UltraScale+

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

SMPTE SD/HD/3G-SDI (3.0)

*Version 3.0 (Rev. 6)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

SMPTE UHD-SDI (1.0)

*Version 1.0 (Rev. 1)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

SMPTE2022-5/6 Video over IP Receiver (5.0)

*Version 5.0 (Rev. 2)

*Added support for Zynq UltraScale+ MPSoC, Kintex UltraScale+ and Virtex UltraScale+

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Fixed video output stopped after few frames on core that generated without Forward Error Correction (FEC) Engine

SMPTE2022-5/6 Video over IP Transmitter (4.0)

*Version 4.0 (Rev. 4)

*Added support for Zynq UltraScale+ MPSoC, Kintex UltraScale+ and Virtex UltraScale+

*Updated the demonstration test bench to have latest VOIP_RX simulation model

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

SPI-4.2 (13.0)

*Version 13.0 (Rev. 7)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

SelectIO Interface Wizard (5.1)

*Version 5.1 (Rev. 6)

*Added option for IODELAYCTRL and BUFG

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Serial RapidIO Gen2 (4.0)

*Version 4.0 (Rev. 1)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Added data streaming feature.

Soft Error Mitigation (4.1)

*Version 4.1 (Rev. 5)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

System Cache (3.1)

*Version 3.1 (Rev. 2)

*Updated family names for additional UltraScale devices

*Fixed potential dead-lock for rare cases with delayed write

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Ensure that S10_AXI_CRRESP is connected, no functional change

System Management Wizard (1.2)

*Version 1.2 (Rev. 2)

*GUI Related Updates. No Functional Changes.

*Updated RTL to fix CDC warnings

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*UltraScale Plus device support added.

*Generation of input stimulus is changed. Now each input can be fed with unique wave.

*Instantiation of Slave SYSMONs are made optional.

Timer Sync 1588 (1.2)

*Version 1.2 (Rev. 3)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Tri Mode Ethernet MAC (9.0)

*Version 9.0 (Rev. 2)

*Kintex, Virtex and Zynq UltraScale Plus beta support

*Refactored RTL to enable Artix 7 device support for 2.5G data-rates. Updated relevant demo test-bench and XDC files accordingly

*Changed the process of updating RX Oversized frame counter. The new behavior is as follows for an RX frame having size greater than the legal IEEE limit - If Jumbo frames are enabled, then the counter increments irrespective of the RX MAX_LENGTH register value.  If Jumbo frames are not enabled then the counter will increment IFF the RX frame length is less than or equal to RX MAX_LENGTH register value

*Fixed bug in which some of the AXI4_Lite Management signals are present at the block level but are not propagated to the wrapper file

*Updated Example Design XDC to provide sample LOC constraints for IOs and clock elements, for device xcku040 ffva1156; Updated ODELAYE3 fixed delay value for RGMII TXC for this device

*UltraScale Plus device support is limited to simulation only. Timing violations may bee seen when implementing the IP on UltraScale Plus devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

UltraScale FPGAs Transceivers Wizard (1.6)

*Version 1.6

*Added support for UltraScale+ devices and their serial transceiver architectures

*Improved performance of GTY transceivers via parameter updates

*Added new transceiver configuration preset options, and adjusted some existing transceiver configuration presets

*Added support for all QPLL feedback divider values, providing extensive reference clock frequency options for any given line rate

*Added a QPLL Fractional-N calculator feature to the Wizard customization GUI to assist with setting the fractional part of the QPLL feedback divider when enabled

*Raised the maximum frequency of the free-running and DRP clock for some target devices

*Expanded and reorganized portions of the Wizard customization GUI Transmitter Advanced and Receiver Advanced sections

*Added guidance text to the Equalization mode portion of the Wizard customization GUI Receiver Advanced section

*Restricted the Termination value to FLOAT when Link coupling is DC for some target devices

*Improved reliability of reset controller helper block gtwiz_reset_tx_done_out and gtwiz_reset_rx_done_out indicators in the event of PLL lock loss, by changing from bit synchronizer to active-Low reset synchronizer

*Improved reliability of reset controller helper block control of RX programmable divider resets by asserting RXPROGDIVRESET upon RX reset and releasing it after RX CDR lock

*Changed to per-channel bit synchronization of TXRESETDONE and RXRESETDONE for use in the reset controller helper block to address the report_cdc CDC-10 message and to further mitigate the unlikely possibility of a glitch on those inputs

*Added a synchronizer stage to the user clock active indicator output of the transmitter and receiver user clocking network helper blocks

*Fixed a bug that incorrectly forced the enablement of gtwiz_userclk_tx_reset_in for some configurations targeting UltraScale GTH transceivers

*Updated the CPLL calibration module to address a reliability issue with PCIe use modes in Kintex UltraScale ES2 and Virtex UltraScale ES1 devices

*Updated the CPLL calibration block inclusion list to include Virtex UltraScale VU440 ES2 devices by default

*Virtex UltraScale production status is now determined automatically, to simplify support for future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

UltraScale Soft Error Mitigation (3.0)

*Version 3.0

*All monolithic (except KU025) and SSI devices supported

*Add support for error classification feature for all SSI devices

*Add the following new error detection features - Detect-only and Diagnostic Scan

*Resolved AR64513, query command using Linear Frame Addressing to SLR1 of KU115 now functions correctly

*Consistently halt scanning of the configuration memory when IP is in Idle state regardless of why the IP entered the state (uncorrectable error, commanded, etc)

*Modify behavior of IP to not transition to injection state if error injection feature is disabled

*Change minimum clock period to 5714ps (175MHz) in the GUI to align with maximum ICAP clock period for UltraScale -1LV (0.90V) devices

*Generate additional debugging information in error detection report.  See PG187 for modified error detection report.

*Remove the following unused IP parameters - INTERFACE, ENABLE_CONFIG_SCAN, MEMORY_TYPE, MEMORY_IO_TYPE, LOCATE_HELPER_BLOCKS

*Hardware verification performed on KU040, VU095, KU060 ES2, KU115, VU190 ES2  and VU440 ES2 devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

UltraScale+ PCI Express Integrated Block (1.0)

*Version 1.0

*Initial release

*Dedicated PERST is not supported for the Beta release

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.1)

*Version 4.1

*Added support for sfva784 package for xcku035 and xcku040 devices

*Added support for VCU108 Xilinx Development board

*Added option to select MSI or MSI-X capability structure

*Added option to select the Receiver Detect mode (default of Falling Edge)

*For EXTERNAL PIPE INTERFACE mode, a new file xil_sig2pipe.v is delivered in the simulation directory and it replaces the phy_sig_gen.v. BFM/VIPs should interface with the xil_sig2pipe instance in board.v

*Added support for new KintexU and VirtexU devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

VIO (Virtual Input/Output) (3.0)

*Version 3.0 (Rev. 9)

*family name change - zynqplus and virtexplus

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Video Deinterlacer (4.0)

*Version 4.0 (Rev. 9)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Video In to AXI4-Stream (4.0)

*Version 4.0

*Major revision of core to v4.0

*Optimized architecture for speed

*Replaced internal FIFO with FIFO generator IP

*Removed user parameter for hysteresis level

*Added user parameter for component width conversion

*Added user parameter option for synchronous or asynchronous clock mode

*Added overflow and underflow ports

*Added support for Zynq and Kintex UltraScale+ devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Video On Screen Display (6.0)

*Version 6.0 (Rev. 9)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Video Processing Subsystem (1.0)

*Version 1.0

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Video Scaler (8.1)

*Version 8.1 (Rev. 6)

*Added support for Zynq and Kintex UltraScale+ devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Video Test Pattern Generator (7.0)

*Version 7.0

*Completely redesigned IP using Vivado HLS (along with new drivers)

*Support added for 1, 2, or 4 samples per clock enabling 4K 60fps

*Support added for 16 bits per video component

*AXI4-Lite interface required (using the driver with a processor) to configure/initialize the core

*Three video components supports RGB, YUV 4:4:4, YUV 4:2:2, and YUV 4:2:0

*Optional Video Timing Controller interface removed

*One single clock and reset for entire IP

*Clock Enable removed

*Optional INTC ports removed

*Added TKEEP, TSTRB, TID, and TDEST to AXI4-Stream

*Some ports renamed - aclk to ap_clk, aresetn to ap_rst_n, irq to interrupt and s_axi to s_axi_CTRL

*Demonstration Test Bench replaced by an Example Design

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Video Timing Controller (6.1)

*Version 6.1 (Rev. 6)

*Fixed interlaced video field generation

*Fixed interlaced video and field-id polarity detection

*Added generator source select for interlaced video to control register

*Fixed vsync generation porch width offset issue

*Added support for Zynq and Kintex UltraScale+ devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Video over IP FEC Receiver (1.0)

*Version 1.0 (Rev. 1)

*IP sub cores blk_mem_gen and fifo_generator updated with new version

*Removed core_clk FREQ range

*Added support for Zynq UltraScale+ MPSoC, Kintex UltraScale+ and Virtex UltraScale+

Video over IP FEC Transmitter (1.0)

*Version 1.0 (Rev. 2)

*IP sub cores blk_mem_gen and fifo_generator updated with new version

*Removed core_clk FREQ range

*Added support for Zynq UltraScale+ MPSoC, Kintex UltraScale+ and Virtex UltraScale+

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.1)

*Version 4.1

*For EXTERNAL PIPE INTERFACE mode, a new file xil_sig2pipe.v is delivered in the simulation directory and it replaces the phy_sig_gen.v. BFM/VIPs should interface with the xil_sig2pipe instance in board.v

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

Viterbi Decoder (9.1)

*Version 9.1 (Rev. 4)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

XADC Wizard (3.2)

*Version 3.2

*Corrected the Alarm limits for VCCINT and VCCBRAM for -1L speedgrade devices.

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*IP delivers only Verilog example design files.

XAUI (12.2)

*Version 12.2 (Rev. 2)

*Updated to use the latest GT UltraScale Wizard v1.6

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Added support for UltraScale plus devices

*Added support for xcku095 device family

YCrCb to RGB Color-Space Converter (7.1)

*Version 7.1 (Rev. 6)

*Supported devices and production status are now determined automatically, to simplify support for future devices

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores

ZYNQ UltraScale+ MPSoc (1.0)

*Version 1.0 (Rev. 1)

*Added IO pad report

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

ZYNQ7 Processing System (5.5)

*Version 5.5 (Rev. 3)

*Added unit (cycles) to Precharge Time column for DDR Controller

*PS internal connectivity updated with EMIO_GPIO signals

*PCW output code updates - Added volatile keyword for register access

*Clock correction for S_AXI_HP3 interface

*Parameters are added for ps7_ddr_0, ps7_ram_0 and ps7_ddr_ram_1 peripherals

*memory ranges depending on its interface name

*Following is the list of parameter which will get populated based on its interface HP/GP or ACP

*C_HP0_AXI_BASENAME, C_HP0_AXI_HIGHNAME

*C_HP1_AXI_BASENAME, C_HP1_AXI_HIGHNAME

*C_HP2_AXI_BASENAME, C_HP2_AXI_HIGHNAME

*C_HP3_AXI_BASENAME, C_HP3_AXI_HIGHNAME

*C_GP0_AXI_BASENAME, C_GP0_AXI_HIGHNAME

*C_GP1_AXI_BASENAME, C_GP1_AXI_HIGHNAME

*C_ACP_AXI_BASENAME, C_ACP_AXI_HIGHNAME

*Updated description for Tie off AxUSER under PS - PL Configuration -> ACP Slave AXI Interface

*SDIO CD & WP are routed to EMIO when not used.

*New parameter PCW_PLL_BYPASSMODE_ENABLE introduced to put PLLs in bypass mode

*New attributes as MASTERBUSINTERFACE  and SLAVEBUSINTERFACE  added to Processing System

*internal slave/master memory ranges

*Fixed SMC timing calculations

*Fixed reg_ddrc_pre_cke_x1024 calculation while DRAM RST is still asserted

*Fix for WSTROBE (NIC301) for SDIO in PS7 wrapper

ZYNQ7 Processing System BFM (2.0)

*Version 2.0 (Rev. 5)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

axi_sg (4.1)

*Version 4.1 (Rev. 2)

*Mark Debug attribute removed from core hdl

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

interrupt_controller (3.1)

*Version 3.1 (Rev. 2)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

lib_bmg (1.0)

*Version 1.0 (Rev. 2)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

lib_cdc (1.0)

*Version 1.0 (Rev. 2)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

lib_fifo (1.0)

*Version 1.0 (Rev. 3)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

lib_pkg (1.0)

*Version 1.0 (Rev. 2)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

lib_srl_fifo (1.0)

*Version 1.0 (Rev. 2)

*IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

*Revision change in one or more subcores