UltraScale designs using GTH/GTY in buffer bypass mode might see phase alignment not complete after initialization.
TXPHALIGNDONE or RXPHALIGNDONE might not get asserted or remain unstable resulting in data errors on the parallel data bus. Failure is seen on buffer bypass single lane auto mode, but "multiple lane" and "manual" mode are also impacted.
This is because the Vivado 2015.3 or earlier UltraScale Transceiver Wizard sets the RATE_SW_USE_DRP attribute wrongly.
The RATE_SW_USE_DRP attribute is a PCIe protocol only attribute which controls the buffer bypass path in UltraScale GTH and GTY. The RATE_SW_USE_DRP attribute should be set to 1'b1 for non-PCIe protocol use case.
The PCIe interface is not impacted by this issue. Non-PCIe interfaces (such as CPRI, Original protocol) which uses buffer bypass function are impacted.
Designs using UltraScale Kintex/Virtex GTH and GTY on non-PCIe protocols should manually change the RATE_SW_USE_DRP signal to 1'b1 by overriding this attribute on the Transceiver wizard generated XDC.
The Vivado 2015.4 UltraScale Transceiver Wizard will set this attribute correctly by default.