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AR# 65588

AXI Bridge for PCI Express v2.5 (Rev2) (Vivado 2014.4) - Timing issue with post-synthesis DCP implementation

Description

Version Found: v2.5 (Rev2)

Version Resolved and other Known Issues: See (Xilinx Answer 54646)

When implementing the post-synthesis DCP of AXI Bridge for PCI Express core example design in Vivado 2014.4, for an XC7V2000TFLG1925-1 device, the tool reports timing failure.

The following steps were followed:

1. I Open the post-synthesis DCP file of the example design.

2. I run the following commands:

opt_design -directive Explore
place_design -directive Explore
phys_opt_design -directive AggressiveExplore
route_design -directive Explore

The place_design puts MMCM on X0Y11 instead of X1Y1 which results in timing failure.

When implementing the design without opening a DCP file, no timing failure is reported.

Solution

To resolve the issue, set a LOC constraint on the MMCM so that it will be placed in the same clock region as the PCIe GT_COMMON primitive.

Note: "Version Found" refers to the version the problem was first discovered.

The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

10/08/2015 - Initial Release

AR# 65588
Date Created 10/07/2015
Last Updated 10/15/2015
Status Active
Type Known Issues
IP
  • AXI PCI Express (PCIe)