In HLS, I can do C and C/RTL co-simulation on my accelerator to quickly verify functionality.
I am now designing an accelerator as part of my system using SDSoC.
Is there a C simulation flow? How should I verify functionality?
There is currently no fully integrated simulation flow for fundamental reasons.
HLS is mapping C code to hardware as a single, standalone unit with no hardware dependencies. as a result, C-based simulation is mostly straightforward on a host machine.
However, SDSoC is doing the same thing but also adding datamover logic, running software/drivers on the target processor (i.e. ARM). It is very much dependent on the underlying hardware and therefore running simulation on a host machine is not as simple.
The recommended flows for functional verification with SDSoC designs are:
1) Build the design with no accelerators and run it on the board. This is essentially the same thing as the C-based simulation flow, but it is running on the target processor instead of the host.
2) If you wish to test the HLS accelerators, you can use #ifdef macros to replace SDSoC library calls with C standard lib calls (i.e. sds_alloc with malloc, etc) so that the accelerator code can be simulated on the host using HLS.