We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65642

Termination scheme for disabled clocks at the reference clock input of GTH Transceiver


I am using the XC7VX550T and have connected most of the GTH reference clocks.

However not all of the clocks are used in the FPGA, so the termination is disabled.

This results in a decreased load of the clock buffer and therefore an increased differential voltage swing on the input of the reference clock.

The following is occurring:

1 GTH ref clocks are applied to the input of the FPGA and they are enabled in the FPGA.

2. GTH ref clocks are applied to the input of the FPGA but they are not enabled in the FPGA so the termination is also disabled.

In the first situation the clock stays within the specs stated in the referenced document.

In the second situation the clock exceeds the 2000 mV specification due to the missing termination.

How can I resolve this situation?


It is not recommended to exceed the voltage swing stated in the DC and Switching Characteristics when the reference clock input in not used in the FPGA.

One way to resolve this situation is to connect these disabled clocks to some dummy logic in the design so that the termination will stay enabled, and when required these inputs can be used as input clocks for GT.

AR# 65642
Date 11/05/2015
Status Active
Type General Article
  • Virtex-7