AR# 65647

AXI Memory Mapped to PCI Express v2.7 (Vivado 2015.3) - Erroneous result when the core recieves MSI packet when other traffic is in progress


Version Found: v2.6 (Rev2)
Version Resolved and other Known Issues: See (Xilinx Answer 54646)

The core may run into erroneous state if it receives MSI packet when other packets (MWr, Cfg) are in progress.

This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) - Xilinx Solution Center for PCI Express


This is a known issue to be fixed in a future release of the core. 

To resolve the issue, please install the patch attached to this answer record as described below.

  • The provided patch is for Vivado 2015.3 for the AXI Memory Mapped to PCI Express core.
  • Unzip the attached zip file to the directory of your choice.
  • Open Vivado 2015.3 and create a new project.
  • Open IP catalog. Right click the core you are using and choose IP Settings.
  • Click Add Repositories and point it to the location where you have unzipped the patch.
  • Click OK and you are now ready to generate the core.
  • If you have previously generated the core, you can choose 'Upgrade IP' on your core.
  • Alternatively, you can use the MYVIVADO environment variable and point this to the location of the patch.

After the patch is installed, the version of the AXI Memory Mapped to PCI Express core should indicate: v2.7 (Rev. 1).

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

10/14/2015 - Initial release


Associated Attachments

Name File Size File Type 1 MB ZIP
AR# 65647
Date 11/18/2015
Status Active
Type Known Issues