UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65651

RLDRAM3 IP - Read Latency of 17 is not a valid value for "-093E' parts

Description

Version Found: v1.0

Version Resolved: See (Xilinx Answer 58435)

When configuring the RLDRAM3 IP v1.0 in Vivado 2015.3, a Read Latency value of 17 can be selected when targeting RLDRAM3 parts with the "-093E" speed grade and using a targeted frequency between 938ps and 1070ps. 

However, a Read Latency of 17 is not valid value as the RLDRAM3 IP v1.0 does not support 1200MHz parts at this time.

Solution

Data errors will occur if a Read Latency of 17 is selected.

Please choose a different value.

Revision History:

10/12/2015 - Initial Release

AR# 65651
Date Created 10/12/2015
Last Updated 10/19/2015
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale