AR# 65688


Design Advisory for Zynq-7000 PS DDR - High temperature derating may be insufficient for LPDDR2 DRAM


When an Operating Temperature of High is selected in the DDR Configuration tab of the Zynq-7000 configuration GUI, the refresh and other timing parameter derating will not occur if requested by the LPDDR2 DRAM device.


When choosing the High Operating temperature for LPDDR2, the only modification made is to double the rate of refreshes, which is the correct handling for DDR3/3L/2 DRAM. 

However, LPDDR2 has a more sophisticated mechanism where the DRAM can request further derating from the memory controller. 

The PS DDR controller does not query the DRAM MR4 configuration register for this status and so will not further derate the refresh and other timing parameters.

To work around this issue, the automatic query and derating logic can be manually enabled in the ps7_init.c/tcl files using the following three registers:

  • Set ddrc.lpddr_ctrl0.reg_ddrc_derate_enable(0xF80062A8[2]) to 1.
    This register will enable the reading of the MR4 configuration register and the derating of timing parameters, if requested by DRAM.

  • Set ddrc.lpddr_ctrl1.reg_ddrc_mr4_read_interval(0xF80062AC[15:0]) to 0x29F0.
    This register controls how often the MR4 register is accessed and may be modified from this default as desired.

  • Set ddrc.Two_rank_cfg.reg_ddrc_t_rfc_nom_x32(0xF8006004[11:0]) to double the value chosen with a High setting.
    Because the DRAM will be queried for refresh derating, the normal refresh time can be used.

This issue does not affect DDR3/3L/2 DRAM.

This issue is currently planned to be fixed in Vivado 2016.1. 

A fix to EDK XPS is not currently planned.

Revision History:

11/02/2015 - Initial Version

AR# 65688
Date 10/30/2015
Status Active
Type Design Advisory
Tools More Less
People Also Viewed