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AR# 65697

2015.3: Upgrade of IP Integrator Board flow design from an older version to 2015.3 causes the GPIO & IOMODULE blocks to lose their port properties in the block design


I am using the Vivado board flow and upgrading a project from an older version to Vivado 2015.3. 

If the project uses any of the GPIO/IOMODULE IPs, all IP customization pertaining to the board interface is lost, and the default configuration of the IP is restored.

How do I resolve this?


To resolve this issue, follow the steps below.

1. Upgrade the "project device" to the latest board file version of the same board, available in Vivado 2015.3

2. Upgrade the IPs as prompted by Vivado [In the Vivado GUI, select Tools -> Report -> Report IP Status and then, in the IP Status report click the "Upgrade Selected" button]

3. Check that the board interfaces in individual IPs are the same as earlier. This brings the Block Design to the same state as it was in the earlier version of Vivado.

AR# 65697
Date 01/18/2016
Status Active
Type Known Issues
  • Kintex UltraScale
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.3
  • AXI General Purpose IO
Boards & Kits
  • Kintex UltraScale FPGA KCU105 Evaluation Kit
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