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AR# 65727

Vivado Sysgen - In some configurations of the FIR Compiler, the GUI silently changes the users implementation type due to parameter dependencies


When implementing a half-band filter (because of the coefficients I am loading, I have selected 'Half Band' symmetry), the filter is using too many DSP slices.

Sysgen is reverting back to a 'symmetric' implementation of the filter instead of half-band, which I had applied in the properties of the IP core.

Instead of changing to Symmetry implementation with no notification, the IP cores GUI should return a DRC error when I try to select a half band filter implementation with illegal coefficients.


This is a known issue which has been fixed in Vivado 2015.3.

A DRC is returned when entering the values in the IP GUI.

AR# 65727
Date 10/20/2015
Status Active
Type General Article
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4.1
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  • Vivado Design Suite - 2014.4
  • System Generator for DSP
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