The RGMII specification would need a would need a minimum value of 1ns for TsetupR/TholdR.
This will compute for a total data valid window of 2ns. Does the GMII to RGMII IP comply with this specification?
The GMII to RGMII IP does not meet the minimum requirement as recommended by the specification.
How does it fail: It fails because it cannot meet the input setup/hold constraints as specified in the RGMII v2 spec.
When you change the input delay values to match the spec, HOLD violations are seen on the path from the input pin to the IDDR element. This timing path is within the IOB which implies a fixed route and component delays.
It also implies the following:
Margins: Worst case HOLD slack is negative 1.229 ns which is seen on the path rx_ctl pin to its corresponding IDDR element.
The worst case data window size is 1.915 ns which is 85 ps less than the spec mentioned data-window of 2 ns.
How to minimize this issue: As mentioned before, this failing timing path is in IOB. As such, you do not have a lot of control over how the routing is done.
In order to close timing, you have the following options: