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AR# 65753

2015.3 IPIWARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /processing_system7_0/S_AXI_HP0(0) and /axi_mem_intercon/s00_couplers/auto_pc/M_AXI(4)


I have a design connected up similarly to the following example:

When I validate the design, I receive the following warnings:

Why are the warnings being generated?


The upsizer is removing the USER signals because the AXI specification does not define how width conversion of USER should occur.

As a result it acts conservatively and removes them, which triggers this warning for the user to check.

For the AXI DMA, USER bits are created by the AXI when operating in multi-channel mode.

There is a register that you can write that will put a particular value on that USER bus.

However, because upsizing is occurring, that value should be removed.

Generally this is not a problem, as the Zynq HP port does not look at USER, but it is a valid warning to make sure that you are not expecting to lose USER.

AR# 65753
Date 10/28/2015
Status Active
Type General Article
  • FPGA Device Families
  • Zynq UltraScale+ MPSoC
  • Zynq-7000
  • Zynq-7000Q
  • Vivado Design Suite
  • AXI Interconnect