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AR# 65764

Vivado Synthesis - Parameterized Instantiation is not supported for bottom-up OOC flow

Description

I have a module instantiated twice in the top level, with one port width parameterized.


 module_a ( addr, ...... );
   parameter  width = 2;
   input [width * 7-1 :0]  addr;
   ......
 endmodule

 top  ( ...... );
   wire [6:0] addr1;
   wire [13:0] addr2;
   .....
   module_a  #(
          .width(1))
   inst_1 (
          .addr (addr1);
          ......);
   module_a  #(
          .width(2))
   inst_2 (
          .addr (addr2);
          ......);
 endmodule

I am using bottom-up Out OF Context (OOC) flow as described below:

  1. Synthesize module_a standalone in OOC mode and generate its OOC DCP.
  2. In the top level project, set module_a as black box and add its DCP to the sources.
  3. Run Synthesis and Implementation for the top level.

However, I receive the following Warning and Error in opt_design.

Warning: [Opt 31-155] Driverless net xxx is driving LUT input pin I1 which is used by the LUT equation. If the LUT is not removed or a driver added, this warning will become an error. LUT cell name: uuu

ERROR: [Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: zzz

By examining the netlist schematic, I see that the higher 7 bits [13:7] of addr signal for inst_2 are lost in the top level, which caused the error.

Is this a tool issue?

Solution

This is not a tool issue but incorrect usage.

Parameterized instantiation is not supported in bottom-up OOC flow.

Any parameter propagation in the instantiation of the OOC module, including parameterized port size, is not supported.


In this case, the code can be modified as follows:


 module_a ( addr, ...... );
   input [6 :0]  addr;
   ......
 endmodule

 module_b ( addr, ...... );
   input [13 :0]  addr;
   ......
 endmodule

 top  ( ...... );
   wire [6:0] addr1;
   wire [13:0] addr2;
   .....
   module_a   inst_1 (
          .addr (addr1);
          ......);
   module_b   inst_2 (
          .addr (addr2);
          ......);
 endmodule

AR# 65764
Date Created 10/22/2015
Last Updated 04/05/2016
Status Active
Type Known Issues
Tools
  • Vivado Design Suite