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AR# 65776

UltraScale FPGA Gen3 Integrated Block for PCI Express v4.1 (Vivado 2015.3) - ERROR: [DRC 23-20] Rule violation (REQP-1881) Tandem_design_fails_with_flash_programming

Description

Version Found: 4.1

Version Resolved and other Known Issues: (Xilinx Answer 57945)

Bitstream generation of a Tandem PCIe design in Vivado 2015.3 fails with the following message:

ERROR: [DRC 23-20] Rule violation (REQP-1881) Tandem_design_fails_with_flash_programming - The STARTUPE3 cell <cell name>/U0/startup_i has at least one ACTIVE input pin [ DO[3:0], DTS[3:0], FCSBO, FCSBTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS ] and/or output pin [ DI[3:0] ] which is not compatible with use of the Tandem PROM configuration mode. To resolve this issue tie all the listed input pins of the STARTUP primitive to constant values and leave the listed output pins unconnected.

The following properties are set in the design to enable Tandem PCIe bitstream generation, but the tool still gives the above error message:

set_property HD.TANDEM_BITSTREAMS SEPARATE [current_design]
set_property HD.OVERRIDE_PERSIST FALSE [current_design]


This article is part of the PCI Express Solution Centre:

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express


Solution

This DRC is intended only for Tandem PROM designs as specified in the DRC message itself.

The DRC error does not apply to Tandem PCIe designs.

To resolve the issue, use the following constraint to disable the DRC:

set_property IS_ENABLED FALSE [get_drc_checks REQP-1881]


This DRC should not be disabled for Tandem PROM designs.

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

25/10/2015 - Initial Release

AR# 65776
Date Created 10/23/2015
Last Updated 11/10/2015
Status Active
Type Known Issues
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)