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AR# 65782

JESD204 v6.2 - Rx Core Outputs 0s When Modifying Lanes in Use Register


When the JESD204 v6.2 Lanes in Use register (0x28) is modified from its default value, it causes the output data of all lanes to get tied to 0 and valid data to remain low.


A patch will be released for 2015.3 and the issue will be fixed in Vivado 2015.4. 

Note that if this register does not get modified, the IP works as expected and the use of the patch is not required.

For other JESD known issue, please refer to (Xilinx Answer 61911).

If you have further inquiries on a patch, you can contact Xilinx Technical Support:


AR# 65782
Date 11/02/2015
Status Active
Type General Article
  • JESD204
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