Description

Version Found: DDR4 v1.0, DDR3 v1.0

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

When using the Custom Memory part for DDR3 and DDR3 SDRAM IP the following timing parameters might not get passed down through the IP RTL properly which can impact simulation, hardware and controller efficiency results:

• tZQINIT
• tRRD
• tZQCS
• tFAW

Solution

This issue only occurs when using a Custom Memory part for DDR4 and DDR3 SDRAM IP and does not affect other memory interface types.

To resolve the issue a tactical patch must be installed.

To install the patch, follow one of the methods listed below:

Method 1: (Vivado 2014.4 and later only)

a) Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist).

b) Extract the contents of the ".zip" archive to a directory starting with the name AR65790.

Note: Most extraction tools will allow you to automatically create a directory with the same name as the zip file.

c) Run Vivado software tools from the original install location.

Method 2:

a) Create a separate directory containing patched files.

b) Extract the contents of the ".zip" archive to the desired patch directory location.

c) Set the MYVIVADO environment variable to point to this patch directory.

For example:

set MYVIVADO=C:\MYVIVADO\vivado-patch-AR65790\vivado\

d) Run Vivado software tools from the original install location.

Note: This tactical patch is only compatible with Vivado 2015.3 and DDR4 and DDR3 SDRAM IP v1.0.

Revision History:

10/29/2015 - Initial Release

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