Version Found: 4.1
Version Resolved and other Known Issues: (Xilinx Answer 57945)
When the 'Receiver Detect - Falling Edge' option is selected in the UltraScale FPGA Gen3 Integrated Block for PCI Express /AXI Bridge for PCI Express Gen3 core generation GUI, GT DRP ports should be enabled in the GT Wizard.
However, they are currently disabled.
This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) - Xilinx Solution Center for PCI Express
This is a known issue to be fixed in a future release of the core.
To enable GT DRP ports in Vivado 2015.3, please install the attached patches as described below.
There are two patches provided in this answer record.
For UltraScale FPGA Gen3 Integrated Block for PCI Express, please install AR65831_Vivado_2015_3_preliminary_Ultrascale_Gen3_rev1.zip.
For AXI Bridge for PCI Express Gen3, both patches must be installed.
After the patch is installed, the version of the core should indicate:
Note: "Version Found" refers to the version where the problem was first discovered.
The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
11/05/2015 - Initial Release
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