UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65837

LogiCORE IP DisplayPort v6.1 Sink - What are the lnk_fwdclk_p/n clock signals that appear when targeting UltraScale devices, and how are they to be used?

Description

What are the lnk_fwdclk_p/n clock signals that appear when targeting UltraScale devices, and how are they to be used?

Solution

The lnk_fwdclk_p and lnk_fwdclk_n clock signals are for the DisplayPort core when targeting UltraScale devices. 

They are used with the DP159 retimer and provide a forwarded reference clock input from the DP159.

When targeting UltraScale, the DisplayPort Sink requires 2 reference clocks.

  • For 1.62Ghz a fixed reference fixed reference clock of 270MHz.
  • For all other rates, the DisplayPort Sink uses the forwarded clock from the DP159.


Note: The use of the DP159 is required for the DisplayPort Sink. 

This is because the DisplayPort Sink and driver are designed to use the reference clock that is forwarded through the DP159 retimer.

AR# 65837
Date Created 11/03/2015
Last Updated 11/10/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2015.3
IP
  • DisplayPort