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AR# 65848

Will Vivado Synthesis support global signals in VHDL? (signals declared in a package)


Global signals are signals declared in a package that are usable by any module that refers to this package without having to go through the ports.

They are also called virtual signals and are considered very practical for debug signals.

Will Vivado Synthesis support this construct?


No, there are no plans to support this. It is deemed too risky and a bad design practice.

If a lot of demand is shown to exist for the feature, this decision might be reconsidered.

For more information either create a service request with Xilinx Technical Support and refer to this Answer Record or add a comment on the following forum thread:


AR# 65848
Date 11/11/2015
Status Active
Type General Article
  • Vivado Design Suite
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