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AR# 65875

Zynq UltraScale+ MPSoC - PS-GTR: Multi-lane Link Alignment of PCIe Might Require Greater Than One SKP Ordered Set

Description

The PS-GTR block might repeat or drop two bytes of data during multi-lane link alignment, causing data corruption in the controller for PCIe. 

The corruption continues until the next SKP ordered set (OS) is received. PCIe protocol is capable of handling such errors by re-transmitting the packets that have not been received by the connected device. 

No work-around is necessary. There is no impact on PCIe performance.

PCIe protocols support multi-lane links. In the RX direction, all of the lanes need to be aligned to each other. While this alignment is happening, there is a chance that some data (2 bytes) might be dropped or repeated for one cycle. 

This repetition/dropping of a cycle worth of data will cause the descrambler in the PCIe Controller to get out of sync from the Scrambler in the connected device. As a result all subsequent packets will be corrupted. The data corruption continues until the next SKP OS. 

PCIe mandates SKP OS be transmitted after every 1536 symbols (or 768 cycles). If a packet is received in the first 768 cycles of link up, it has a chance of getting corrupted. If a packet does get corrupted, it will not be ACKed by the PCIe block to the connected device. The connected device will (based on its Replay Timer) re-send the packet. By this time, the data corruption would have ended. The transmitter of the packet (connected component) will log the retry as a correctable error and report to software (if enabled). As a result, the host will have knowledge of this event.

Another side-effect of the bug is that SKP OS that is received right after a string of FTS Ordered Sets (upon wakeup from L0s) is corrupted. This corrupted SKP OS has the same effect on the descrambler and causes packet corruption. This condition is also corrected when the next SKP OS is received (in under 768 cycles).

Solution

Impact:
Minor, this error happens during initial link formation or any link retraining event.
This issue does not impact PCIe performance and does not affect the normal operation of the PCIe IP once the link has come up.
Work-around: PCIe protocol is capable of handling such errors by re-transmitting the packets that have not been received by the connected device, so no work-around is necessary.
See (Xilinx Answer 68750) for a summary of errata work-arounds.
Configurations Affected:PS-GTR in PCIe configuration.
Device Revisions Affected:All Zynq UltraScale+ MPSoCs
AR# 65875
Date 06/22/2017
Status Active
Type Design Advisory
Devices
  • Zynq UltraScale+ MPSoC
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