Simulation of an Aurora 8B10B example fails during the elaboration stage with the following error:
This issue applies to an Aurora 8B10B 4-byte core targeting 7 series GTH/GTP.
Update the following in the <component_name>_gtrxreset_seq.v[hd] file.
Delete the STABLE_CLK port and make a wire initialized to 1'b0 as shown below.
Update the value of the c_flop_input parameter for the "rst_cdc_sync" and "gtrxreset_in_cdc_sync" synchronizers to 1'b0:
This issue is fixed in the 2015.4 release of Vivado Design Suite.
11/05/2015 - Initial Release
02/24/2016 - Updated to mention about target GT's