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AR# 65940

UltraScale FPGA Gen3 Integrated Block for PCI Express / UltraScale+ FPGA Integrated Endpoint Block for PCI Express - Tandem and Debug Hub Issues

Description

When implementing a design with a Tandem enabled UltraScale FPGA Gen3 Integrated Block for the PCI Express core and MIG or debug IPs, the tool gives the following error during implementation:

[DRC 23-20] Rule violation (HDTC-12) CONFIG cells must be in stage one - Configuration cell 'dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst' is not marked as a stage 1 cell. This cell must be added to stage 1 or removed from your design. You may also need to add additional driving logic to stage 1 as dictated by the desired design behavior. To add this cell to stage 1, please do the following: 
        set_property HD.TANDEM 1 [get_cells dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst]
        add_cells_to_pblock [get_pblocks -of_object [get_sites CONFIG_SITE_X0Y0]] [get_cells dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst]

When implementing a design with a Tandem enabled UltraScale+ Devices Integrated Block for PCI Express core and MIG or debug IPs, the tool gives the following error during implementation:

[DRC HDTC-12] CONFIG cells must be in stage one: Configuration cell 'dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst' is not marked as a stage 1 cell. This cell must be added to stage 1 or removed from your design. You may also need to add additional driving logic to stage 1 as dictated by the desired design behavior. To add this cell to stage 1, please do the following:
    set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst]


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

To resolve this issue, create a Tcl file, add the Tcl file in the tcl.pre* field of the Place Design section in the Implementation settings and then either add the Option 1 OR Option 2 content below in the Tcl File.

 


 

Option 1 (UltraScale): The generic approach

set master_cfg_site [get_sites -of_objects [get_slrs -filter {IS_MASTER==true}] -filter {NAME =~ CONFIG_SITE_*}]
set bscan_cells [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ CONFIGURATION.BSCAN.* } ]
set_property HD.TANDEM 1 $bscan_cells
add_cells_to_pblock [get_pblocks -of_objects [get_sites $master_cfg_site]] $bscan_cells

 

Option 1 (UltraScale+): The generic approach

set bscan_cells [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ CONFIGURATION.BSCAN.* } ]
set_property HD.TANDEM_IP_PBLOCK Stage1_Main $bscan_cells

 

OR

Option 2 (UltraScale) You can use the constraint that is directly listed in the error message

set_property HD.TANDEM 1 [get_cells dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst]
add_cells_to_pblock [get_pblocks -of_object [get_sites CONFIG_SITE_X0Y0]] [get_cells dbg_hub/inst/N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst]

 

Option 2 (UltraScale+) You can use the constraint that is directly listed in the error message

set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst]

 

Note: In incremental flow, run the commands before RCI (read_checkpoint -incremental)

Revision History:

 

  • 11/11/2015 - Initial Release
  • 02/25/2019 - Added UltraScale+ Support and Fixed Typos

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34536 Xilinx Solution Center for PCI Express N/A N/A
57945 UltraScale FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues N/A N/A
AR# 65940
Date 08/15/2019
Status Active
Type General Article
IP
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