Version Found: 4.1
Version Resolved and other Known Issues: (Xilinx Answer 57945)
UltraScale FPGA Gen3 Integrated Block for PCI Express v4.1 gives the following critical warnings during implementation for certain PCIe Block and Quad Locations.
Please scroll down for Table:
|Severity||ID||Description||Depth||Exception||Source (From)||Destination (To)||Category|
|Critical||CDC-1||1-bit unknown CDC circuitry||0||False Path||sys_rst_n||pcie3_i/inst/reg_user_lnk_up_reg/D||Unknown|
|Critical||CDC-7||Asynchronous reset unknown CDC circuitry||0||False Path||sys_rst_n||pcie3_i/inst/user_reset_int_reg/PRE||Unknown|
This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) Xilinx Solution Center for PCI Express
The warning message can be safely ignored. It will be removed in a future release of the core.
Note: "Version Found" refers to the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
11/11/2015 - Initial Release