Version Found: MIG v1.0
Version Resolved: See (Xilinx Answer 58435)
An UltraScale MIG example design which passes calibration successfully with the Vivado Synthesis and Implementation flow might error out in hardware manager with the Synplify PRO Black Box Testing flow provided in (PG150).
A message similar to the following can occur:
This error occurs because the .bmm and .elf files required for calibration have not been associated.
(PG150) Chapter 6 includes a section titled "Synplify Pro Black Box Testing".
This section is missing required steps within this flow to associate the .elf and .bmm files.
Please insert the following steps between the existing steps 9 and 10:
10) Open the Synthesized Design.
11) Associate the .elf and .bmm files using Tcl commands similar to the following:
12. Use the following command:
The following INFO message should now be seen:
13) Run the implementation flow with the Vivado tool.
Note: If multiple instances of the same Memory IP are used in the same design the SCOPED_TO_CELLS constraint should include a list of each instance and use the absolute hierarchy to point to the cell rather than use the SCOPED_TO_REF constraint.
|06/29/2016||Updated to include multiple instances of the same Memory IP|