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AR# 65950

MIG UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs can fail in calibration


Version Found: MIG v1.0

Version Resolved: See (Xilinx Answer 58435)

An UltraScale MIG example design which passes calibration successfully with the Vivado Synthesis and Implementation flow might error out in hardware manager with the Synplify PRO Black Box Testing flow provided in (PG150). 

A message similar to the following can occur:

WARNING: [Xicom 50-46] One or more detected MIG version registers have empty values: MIG properties will not be built.
Parameter Map Version: 2, Error Map Version: 0, Calibration Map Version: 0, Warning Map Version: 0
Invalid calibration version register value detected from MIG core: 000.


This error occurs because the .bmm and .elf files required for calibration have not been associated.

(PG150) Chapter 6 includes a section titled "Synplify Pro Black Box Testing".

This section is missing required steps within this flow to associate the .elf and .bmm files.

Please insert the following steps between the existing steps 9 and 10:

10) Open the Synthesized Design.

11) Associate the .elf and .bmm files using Tcl commands similar to the following:

  1. set_property SCOPED_TO_REF core_name_ddr4_mem_intfc [get_files *.elf]
  2. set_property SCOPED_TO_CELLS u_ddr_cal_riu/mcs0/microblaze_I [get_files *.elf]
  3. set_property SCOPED_TO_REF core_name_ddr4_mem_intfc [get_files *.bmm]
  4. set_property SCOPED_TO_CELLS u_ddr_cal_riu/mcs0 [get_files *.bmm]

12. Use the following command:


The following INFO message should now be seen:

Generating merged BMM file for the design top 'ddr4_0_stub'...

INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: <ELF Path>/calibration_ddr.elf

refresh_design: Time (s): cpu = 00:01:13 ; elapsed = 00:00:57 . Memory (MB): peak = 8296.516 ; gain = 61.012 ; free physical = 684 ; free virtual = 103414

13) Run the implementation flow with the Vivado tool.

Note: If multiple instances of the same Memory IP are used in the same design the SCOPED_TO_CELLS constraint should include a list of each instance and use the absolute hierarchy to point to the cell rather than use the SCOPED_TO_REF constraint.

For example:

add_files /<location of *.elf file>/calibration_ddr.elf
add_files /<location of *.bmm file>/microblaze_mcs_ddr.bmm
set_property SCOPED_TO_CELLS {<inst0>/u_ddr_cal_riu/mcs0/microblaze_I <inst1>/u_ddr_cal_riu/mcs0/microblaze_I <inst2>/u_ddr_cal_riu/mcs0/microblaze_I <inst3>/u_ddr_cal_riu/mcs0/microblaze_I} [get_files calibration_ddr.elf]
set_property SCOPED_TO_CELLS {<inst0>/u_ddr_cal_riu/mcs0 <inst1>/u_ddr_cal_riu/mcs0 <inst2>/u_ddr_cal_riu/mcs0 <inst3>/u_ddr_cal_riu/mcs0} [get_files microblaze_mcs_ddr.bmm]

Revision History:

06/29/2016Updated to include multiple instances of the same Memory IP
11/16/2015Initial Release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 65950
Date 07/13/2016
Status Active
Type Known Issues
  • Virtex UltraScale
  • Kintex UltraScale
  • Vivado Design Suite
  • MIG UltraScale