We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65987

High Speed SelectIO Wizard - TX - TX_GATING attribute incorrectly set.


Version Found: 2015.3

The TX_GATING attribute combined with the TBYTE_IN pin controls the bring up of the TX Bitslices.

If the TX_GATING attribute is set to FALSE, channels can become mis-aligned. This affects TX or bidirectional designs.

Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)


This issue is resolved in version 3.0 of the High Speed SelectIO Wizard, included in the 2016.1 release.

To work around this issue in older versions, set the TX_GATING Attribute to ENABLE.

This can be done using the following constraint in the XDC file (note that the hierarchy will need to be changed to the specific user set-up):

set_property TX_GATING ENABLE [get_cells {<path_of_the_core_in_the_design>/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[*].bs_ctrl_inst}]

The approach above will not take effect in a behavioral simulation. If this is an issue, the following approach can be used:

Update the HDL file in the following location using the flow described in (Xilinx Answer 57546):


If necessary, the edited IP can be packaged up and re-used. For more information see (UG1118).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 65987
Date 11/09/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
Page Bookmarked