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AR# 65988: High Speed SelectIO Wizard - TX_RX - Bitslice Control EN_VTC asserted incorrectly
High Speed SelectIO Wizard - TX_RX - Bitslice Control EN_VTC asserted incorrectly
Version Found: 2015.3
The BITSLICE CONTROL EN_VTC port should be controlled only by DLY_RDY until the reset sequence is completed.
The wizard currently allows user control of the bit slice control EN_VTC before the reset sequence completes.
Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
As a work-around you can edit the HDL file in the following location, following the flow described in (Xilinx Answer 57546):