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AR# 65988

High Speed SelectIO Wizard - TX_RX - Bitslice Control EN_VTC asserted incorrectly

Description

Version Found: 2015.3

The BITSLICE CONTROL EN_VTC port should be controlled only by DLY_RDY until the reset sequence is completed. 

The wizard currently allows user control of the bit slice control EN_VTC before the reset sequence completes.


Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)

Solution

As a work-around you can edit the HDL file in the following location, following the flow described in (Xilinx Answer 57546):

...<path_of_the_core_in_the_design>\asbd.srcs\sources_1\ip\high_speed_selectio_wiz_0\hdl\hssio_wiz_top.v


If necessary, the edited IP can be packaged up and re-used. For more information see (UG1118).

The following changes should be made to hssio_wiz_top.v

// Edit for AR http://www.xilinx.com/support/answers/65988.html

   assign n0_en_vtc          = (C_EN_BSC0 == 1) ? ( (rst_seq_done & n0_en_vtc_in) || (! rst_seq_done & bsc_en_vtc) )        : 1'b0;
   assign n1_en_vtc          = (C_EN_BSC1 == 1) ? ( (rst_seq_done & n1_en_vtc_in) || (! rst_seq_done & bsc_en_vtc) )        : 1'b0;
   assign n2_en_vtc          = (C_EN_BSC2 == 1) ? ( (rst_seq_done & n2_en_vtc_in) || (! rst_seq_done & bsc_en_vtc) )        : 1'b0;
   assign n3_en_vtc          = (C_EN_BSC3 == 1) ? ( (rst_seq_done & n3_en_vtc_in) || (! rst_seq_done & bsc_en_vtc) )        : 1'b0;
   assign n4_en_vtc          = (C_EN_BSC4 == 1) ? ( (rst_seq_done & n4_en_vtc_in) || (! rst_seq_done & bsc_en_vtc) )        : 1'b0;
   assign n5_en_vtc          = (C_EN_BSC5 == 1) ? ( (rst_seq_done & n5_en_vtc_in) || (! rst_seq_done & bsc_en_vtc) )        : 1'b0;
   assign n6_en_vtc          = (C_EN_BSC6 == 1) ? ( (rst_seq_done & n6_en_vtc_in) || (! rst_seq_done & bsc_en_vtc) )        : 1'b0;
   assign n7_en_vtc          = (C_EN_BSC7 == 1) ? ( (rst_seq_done & n7_en_vtc_in) || (! rst_seq_done & bsc_en_vtc) )        : 1'b0;
  
//   assign n0_en_vtc          = (C_EN_BSC0 == 1) ? (n0_en_vtc_in || bsc_en_vtc)        : 1'b0;
//   assign n1_en_vtc          = (C_EN_BSC1 == 1) ? (n1_en_vtc_in || bsc_en_vtc)        : 1'b0;
//   assign n2_en_vtc          = (C_EN_BSC2 == 1) ? (n2_en_vtc_in || bsc_en_vtc)        : 1'b0;
//   assign n3_en_vtc          = (C_EN_BSC3 == 1) ? (n3_en_vtc_in || bsc_en_vtc)        : 1'b0;
//   assign n4_en_vtc          = (C_EN_BSC4 == 1) ? (n4_en_vtc_in || bsc_en_vtc)        : 1'b0;
//   assign n5_en_vtc          = (C_EN_BSC5 == 1) ? (n5_en_vtc_in || bsc_en_vtc)        : 1'b0;
//   assign n6_en_vtc          = (C_EN_BSC6 == 1) ? (n6_en_vtc_in || bsc_en_vtc)        : 1'b0;
//   assign n7_en_vtc          = (C_EN_BSC7 == 1) ? (n7_en_vtc_in || bsc_en_vtc)        : 1'b0;

// End Edit for AR http://www.xilinx.com/support/answers/65988.html

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 65988
Date Created 11/17/2015
Last Updated 12/18/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale