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AR# 65990

High Speed SelectIO Wizard - RX - DATA clock defaults to non-invert (INV_RXCLK = FALSE)


Version Found: 2015.3

Currently the High Speed SelectIO wizard generates code with the INV_RXCLK set to FALSE and the user cannot change this using the wizard GUI. In a scenario where the clock is inverted, the interface will not work as expected.

Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)


To work around this issue, set the INV_RXCLK Attribute to TRUE.

This can be done using the following constraint in the XDC file (Note that the hierarchy will need to be changed to the specific user's set-up):

set_property INV_RXCLK TRUE [get_cells {<path_of_the_core_in_the_design>/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[*].bs_ctrl_inst}]

The approach above will not take effect in a behavioral simulation. If this is an issue, the following approach can be used:

Edit the HDL file in the following location, following the flow described in (Xilinx Answer 57546):


If required, the edited IP can be packaged up and re-used. For more information see (UG1118).

The following modifications can be made in bs_ctrl_top.v:

Original code:

        .INV_RXCLK             ("FALSE"),

Modified Code:

       localparam [7:0] INV_RXCLK= 8'b0011_0011  ;//BS[13] is an inverted clock be Nib2, BS0

        .INV_RXCLK             (INV_RXCLK[i] == 1'b1 ? "TRUE" : "FALSE"), //C ("FALSE"),

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 65990
Date 03/22/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
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