Version Found: 2015.3
Currently the High Speed SelectIO wizard generates code with the INV_RXCLK set to FALSE and the user cannot change this using the wizard GUI. In a scenario where the clock is inverted, the interface will not work as expected.
Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
To work around this issue, set the INV_RXCLK Attribute to TRUE.
This can be done using the following constraint in the XDC file (Note that the hierarchy will need to be changed to the specific user's set-up):
The approach above will not take effect in a behavioral simulation. If this is an issue, the following approach can be used:
Edit the HDL file in the following location, following the flow described in (Xilinx Answer 57546):
If required, the edited IP can be packaged up and re-used. For more information see (UG1118).
The following modifications can be made in bs_ctrl_top.v: