AR# 65998

Design Advisory - System Monitor and PCI Express: I2C_SDA, I2C_SCL, PERSTN0 or PERSTN1 I/O pins have lower than expected Pin voltage levels


On the dual purpose pins that can act as I2C_SDA, I2C_SCL, PERSTN0 or PERSTN1 pins for the SYSMONE1 and/or PCIE hard blocks, a 3.3v interface might see a reduction of the maximum "high" voltage to a 2.5V - 2.7V, instead of being allowed to reach the expected 3.3V VCCO level when the bank 65 is operated at VCCO_65=3.3V.


Kintex UltraScale devices include dual-purpose I/O that can provide dedicated connections to the System Monitor I2C interface and the integrated block for PCI Express reset input.

These pin names are documented as IO_L23N_T3U_N9_I2C_SDA_65, IO_L23P_T3U_N8_I2C_SCLK_65, IO_T3U_N12_PERSTN0_65 and IO_T1U_N12_PERSTN1_65 in the Kintex UltraScale pinout tables.

When these I/O are used for their dedicated I2C_SDA, I2C_SCL, PERSTN0 or PERSTN1 function, Vivado 2015.3 or earlier will incorrectly enable a circuit path connecting the I/O to internal low voltage circuits. 

If the I/O is externally connected to 3.3V signaling levels it will result in the external signal not reaching the full logic high voltage level of 3.3V.

How do I identify whether a design is affected?

For a design to potentially be affected, the design must have all of these attributes:

  • UltraScale Kintex KU025, KU035, KU040, KU060, KU085, KU115 device
  • Bitstream generated from Vivado 2015.3, or earlier
  • Operates Bank 65 at 3.3V or 2.5V
  • Includes the SYSMONE1 primitive AND connects the primitives I2C_SCLK/I2C_SDA ports to the I2C_SCLK/I2C_SDA pins, and/or uses UltraScale Gen3 Integrated Block for PCI Express (PCIe) with the PERSTN0 (and/or PERSTN1) pin.

What are the work-around options?

The issue is resolved in Vivado 2015.4 and newer. You can rebuild the design in Vivado 2015.4, or at a minimum, you can use Vivado 2015.4 to write a new bitstream from a design checkpoint (.DCP) file from a prior version of Vivado.

The following Tcl commands can be used to update a design without completely re-implementing the project:

open_checkpoint top_routed.dcp
write_bitstream top_from_2015_4_write_bitstream.bit

The top_routed.dcp in these commands is the routed design checkpoint file from the last implementation directory of a Vivado <project> tree: <project>/*.runs/impl.*/

What designs are NOT impacted?

  • Uses of those pins other than for the dedicated I2C or PERSTN functions (described above) are not affected. i.e. user defined LVCMOS33 I/O, not used as I2C_SDA, I2C_SCL, PERSTN0 or PERSTN1
  • Designs that do not leverage the PCI Express hard block and that do not use the SYSMONE1 block in I2C access mode are not impacted
  • Designs where Bank 65 operates at 1.8V or below are not impacted
  • The KU095 is not affected, Virtex UltraScale, and all UltraScale+ families are not affected
  • Designs where bitstream generation was run in Vivado 2015.4 (or newer)

For more details, please see the Xilinx Customer Notice on this issue:

AR# 65998
Date 11/25/2015
Status Active
Type Design Advisory