Version Found: 2015.3
Reset state machine control requires a continuously running RIU clock source. As a result, an RIU clock cannot be driven by one of the outputs of the PLL clock.
Currently the wizard uses a PLL output for the RIU CLK and this can cause the interface to not come out of reset.
Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
In order to avoid having an extra clock input to feed the RIU clock, or for designs that require the RIU clock to be phase aligned to the PLL outputs, edit the IP to allow the PLL to use an asynchronous reset driven by the reset inputs.
The following is an example of how to edit the core to allow the state machine to work using clock outputs from the PLL:
If needed, the edited IP can be packaged up and re-used. For more information see (UG1118)
3. The solution is to connect the reset directly to the PLL instead of using the PLL reset state machine.
The reset sequence that includes the PLL clock connections should be modified within <path_of_the_core_in_the_design>\ABCD.srcs\sources_1\ip\high_speed_selectio_wiz_0\hdl\clk_rst_top.v:
The following is an example of the hierarchy:
4. After modifying and saving clk_rst_top.v, the core will now need to be synthesized.
Because the core is now managed by the designer this means that the core must be run out of context.
5. After the out of context core has been synthesized, the project can be synthesized using the updated core: