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AR# 66038

2015.4 XPE/Report Power - Routing Complexity


What is "Routing Complexity", introduced in Vivado 2015.4?

How should I use this parameter?


A change has occurred in the Logic page for the 2015.4 and later versions of XPE targeting UltraScale and UltraScale+

The estimator no longer requires the specification of Fanout, and now requests Routing Complexity.

The following is a brief explanation of the change, and recommendations towards its use.


In prior versions of XPE, the tool would estimate routing usage and the associated capacitive load used for dynamic power calculations by using the logical fanout value.
The basic assumption it made was, the more fanout, the more routing resources used and thus more capacitive load.
The problem this presented was that it is possible that a shorter or longer than average route could be used in enough of the design to cause the estimation to be different to what was actually implemented. 

To compensate for this, the specification for routing resources was changed from a logical specification of fanout to a physical implementation of Routing Complexity.
Routing Complexity is a simple factor to say whether the design uses average interconnect usage or can be shifted to be above or below average.
The average value for routing using the Routing Complexity units is 8.00 and that is what the XPE default is set to.


This number could be guided up to 12 if above average routing usage is expected or down to 8 if less than average routing is used.
It is not recommended to go either extremely high or extremely low with the number as it is very rare to have a design as a whole that exceeds 15 or is below 5 (Although individual nets might).

For example, a very high fanout reset net used in a very large FPGA might have a routing complexity that exceeds 20, as it must route to most of the chip.
In general however, nets with this extreme of fanout and associated routing resources are rare.

On the other side of the spectrum, you could have a route that has a fanout of 1 and is placed in the same Slice, which could represent a very low routing complexity.
However this is unlikely to occur on all of the nets in the design as well.

There are several factors that can influence routing complexity including the following:



  • Fanout
  • Device size
  • Design utilization
  • Synthesis and Place and Route options used Floorplanning



If for instance, you expect to have a heavily utilized design, you can guide Routing Complexity up to match that expectation.

Or if you have a highly pipelined and controlled fanout design, you might want to guide routing complexity down.


Once you have a placed and routed design, you can use the Vivado report_power command to create a .xpe that can be imported into XPE which will back-annotate the actual routing complexity for that design in that implementation to XPE for analysis.

This can then be used and compared with other runs to understand how routing influences the overall power consumption  for that design, target device, and tool options.


More documentation and details can be found in (UG440) Xilinx Power Estimator User Guide and are coming soon to (UG949) UltraFast Design Methodology Guide for the Vivado Design Suite.

AR# 66038
Date 12/03/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.4
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