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AR# 66067

v2.0 - I2C - How to handle bus busy signal for a multi-master I2C system?


What is the best method to handle a bus busy signal for a multi-master I2C system?


The user is responsible for ensuring that the bus is not busy if multiple masters are present on the bus.

The following is sample code which can be used as a reference to wait for the busy signal to go down before writing to the slave.

u32 StatusRegister = XIic_ReadReg(DP159_ASE_ADDR, XIIC_SR_REG_OFFSET);
while (( StatusRegister & XIIC_SR_BUS_BUSY_MASK) == XIIC_SR_BUS_BUSY_MASK) {
StatusRegister = XIic_ReadReg(BASE_ADDR, XIIC_SR_REG_OFFSET);

AR# 66067
Date 12/03/2015
Status Active
Type Known Issues
  • Vivado Design Suite
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