The Zynq UltraScale+ MPSoC devices are documented in the Zynq data sheet, technical reference manual and other documents.
Important Design Advisories and other considerations that transcend these documents are listed here.
The source point for technical content is the Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).
Design Advisories Alerted on March 19th, 2018
|(Xilinx Answer 70622)||Design Advisory for Zynq UltraScale+ MPSoC: 2017.x Xilinx Development tools and software re-use the same AES Key and IV pair across multiple partitions.|
Design Advisories Alerted on April 17th, 2017
|(Xilinx Answer 69034)||Design Advisory for 7 Series, UltraScale and UltraScale+, all versions of Vivado prior to 2016.3 failed to include Flight time delays for differential I/O Standards|
|(Xilinx Answer 68615)||Design Advisory for Zynq UltraScale+ MPSoC: Boot from NAND might fail if there is data corruption in the first parameter page|
Design Advisories Alerted on April 10th, 2017
|(Xilinx Answer 68832)||Design Advisory for UltraScale FPGA, UltraScale+ FPGA, and Zynq UltraScale+ MPSoC eFUSE Programming with Vivado 2016.4 (and earlier)|
Design Advisory Alerted on December 5th, 2016
|(Xilinx Answer 68210)||FSBL authenticates the boot image in external DDR|
Design Advisory Alerted on October 17th, 2016
|(Xilinx Answer 67861)||How do I upgrade from Vivado 2016.2 and earlier versions?|
Design Advisory Alerted on April 18th, 2016
|(Xilinx Answer 66944)||Design Advisory for Zynq UltraScale+ MPSoC and Kintex UltraScale+ FPGA - Updated Package Pinouts|