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AR# 66103

Block Memory Generator v12.0 : Width and Depth paramenter settings when BMG IP core is used in “BRAM controller” mode with IP Integrator flow

Description

How do I configure memory port width and depth for the BMG IP used in BRAM controller mode in the IP Integrator flow?

Solution

When using BRAM controller mode in BMG IP, the width/depth of Port-A/B depends on the address range assigned for the AXI BRAM controller and the value of the data width selected in the AXI BRAM controller.

You need to change the data width and address range of the BRAM controller to change the width and depth of the Block memory generator IP.

For example, if you have assigned a 4k (i.e., 4x1024x8 bits = 32768 bits) address range to the AXI BRAM controller, then if you set the data width as 32, the depth will be auto selected as 32768/32=1024.

For the list of supported memory width and depth for the AXI BRAM controller, refer to page 9 Table 1-1 of (PG078).

AR# 66103
Date Created 12/04/2015
Last Updated 12/09/2015
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2015.3
IP
  • Block Memory Generator