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AR# 66109

Zynq UltraScale+ MPSoC, Vivado 2015.4 PinPlanning - How do I perform pin planning for Zynq MPSoC? PS pins do not appear in Package view.


When trying to perform pin planning in Vivado using a Zynq UltraScale+ MPSoC device, the Processing System (PS) pins do not appear in the I/O Ports tab of the Package view and cannot be added in a Pin Planning project. How do I obtain a single pinout which contains both PL and PS pins?


As of Vivado 2015.4, a Vivado Pin Planning project will not be able to import PS mapping information. To obtain a combined package file export of PS and PL pins, the pinout should be obtained by exporting from either a synthesized or implemented design using the File->Export-> Export I/O Ports command.

Due to the increased PS complexity and because the PS pins are controlled via C-code rather than the bitstream, the PS package pins are no longer passed via XDC constraints and the PS ports no longer need to exist in the PL design as was modeled in Zynq-7000.

The handoff of PS pin information such as voltage and I/O standard are now communicated from the PS wrapper HDL (via the PSS_IO attribute string). Vivado will process this attribute and annotate the correct I/O settings in the background during Synthesis. As an improvement to Zynq-7000, logical pin names for the PS pins chosen in the PS IP GUI will now appear in the pinout export.

For example, if a UART0 RX signal is mapped to MIO6, it will now appear as "rxd" or something similar instead of "FIXED_IO[6]".

Additional enhancements to the Zynq MPSoC pin out flow are planned throughout the Vivado 2016 releases.
AR# 66109
Date 12/22/2015
Status Active
Type General Article
  • Zynq UltraScale+ MPSoC
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