Version Found: MIG 7 Series v2.4 Rev1
Version Resolved: See (Xilinx Answer 54025)
When I generate 7 series MIG for a 32 bit wide LPDDR2 component, the instantiation template and mig_7series_0.v generated with MIG IP shows an incorrect width of 19 bits for app_wdf_mask signal.
Due to this incorrect width in mig_7series_0.v file, the below warning is issued during synthesis of the MIG example design.
The width of the app_wdf_mask signal should be 16 bit for a 128 bit wide app_wdf_data signal.
You can copy the below definition and can connect the 16bit input signal to app_wdf_mask and safely ignore the warning message.