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AR# 66162

Zynq-7000 AP SoC - Glitch Might Be Observed On MISO Line Of SPI Controller In Its Master Mode Of Configuration


When SPI is configured in master mode and after the data transfer is complete, a glitch might appear on the MISO line for a short period of time:

The OE signal controlling the 3-State buffer for MISO goes into output mode instead of input which causes this glitch.


Impact: Trivial and does not affect functionality.

Work-around: Setting slcr.MIO_PIN_xx{TRI_ENABLE} = 1, will force the MISO line to always be input and the glitch will not be observed.

Configurations Affected: SPI Controller configured in Master Mode.

AR# 66162
Date 12/09/2015
Status Active
Type Known Issues
  • Zynq-7000
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