AR# 66194


Zynq UltraScale+ MPSoC - Processing System (PS) DDR Controller


This answer record helps you find all Zynq UltraScale+ MPSoC solutions related to the Processing System (PS) DDR Controller known issues.

Note: This answer record is part of Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).

The Xilinx Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to Zynq UltraScale+ MPSoC.

Whether you are starting a new design or troubleshooting a problem, use the Zynq UltraScale+ MPSoC Solution Center to guide you to the right information.


General Guidance/Documentation

Xilinx Answer
(Xilinx Answer 66193)
What are the limitations of the PS DDR controller? Which device should I choose?
(Xilinx Answer 67330)PS DDR Pin Swap Guidelines

Known issues

Xilinx AnswerTitleTool Version FoundTool Version Resolved (Planned)
(Xilinx Answer 65982)Zynq UltraScale+ MPSoC, Vivado 2015.4 - Patch for PS DDR3/DDR4/LPDDR4 and GTR transceiver support2015.4(2016.1)
(Xilinx Answer 66571)Processor System IP GUI Limitations with PS DDR topologies2015.4(2016.1)

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64375 Xilinx Zynq UltraScale+ MPSoC Solution Center N/A N/A

Child Answer Records

Associated Answer Records

AR# 66194
Date 06/07/2016
Status Active
Type Solution Center
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