While using PS + PL designs, no dedicated reset signal is available to reset PL from PS. This answer record documents the work-around for this issue.
Use any of the pins from GPIO as a reset pin with software toggle. Alternatively, use fabric PLL lock signal as reset.
Additionally, while using xsdb as a debugger, please use following set of commands to toggle the GPIO to assert and de-assert reset
dow .<fsbl path>/fsbl.elf
mwr 0xFF0A0018 0xFFFF0000 # Maskable Output Data (GPIO Bank3, EMIO, Lower 16bits)
mwr 0xFF0A02C4 0xFFFFFFFF # Direction mode (GPIO Bank3, EMIO)
mwr 0xFF0A02C8 0xFFFFFFFF # Output enable (GPIO Bank3, EMIO)
mwr 0xFF0A004C 0x00000001 # Output Data (GPIO Bank3, EMIO) # writing 1 to EMIO GPIO 0
#Assert reset (active low) mwr 0xFF0A004C 0x00000000 # Output Data (GPIO Bank3, EMIO) # writing 0 to EMIO GPIO 0
#De-assert reset (active high) mwr 0xFF0A004C 0x00000001 # Output Data (GPIO Bank3, EMIO) # writing 1 to EMIO GPIO 0
Now download ELF file for the PS-PL application
This issue is expected to be fixed in the 2016.1 release.
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