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AR# 66220

Zynq UltraScale+ MPSoC Processing System IP - Reset Signal Availability for PS+PL designs

Description

While using PS + PL designs, no dedicated reset signal is available to reset PL from PS. This answer record documents the work-around for this issue.

Solution

Use any of the pins from GPIO as a reset pin with software toggle. Alternatively, use fabric PLL lock signal as reset.

Additionally, while using xsdb as a debugger, please use following set of commands to toggle the GPIO to assert and de-assert reset


  1. dow .<fsbl path>/fsbl.elf
  2. stop
  3. mwr 0xFF0A0018 0xFFFF0000    # Maskable Output Data (GPIO Bank3, EMIO, Lower 16bits)
  4. mwr 0xFF0A02C4 0xFFFFFFFF  # Direction mode (GPIO Bank3, EMIO)
  5. mwr 0xFF0A02C8 0xFFFFFFFF  # Output enable (GPIO Bank3, EMIO)
  6. mwr 0xFF0A004C 0x00000001   # Output Data (GPIO Bank3, EMIO)  # writing 1 to EMIO GPIO 0                               
  7. After 1000
    #Assert reset (active low)
  8. mwr 0xFF0A004C 0x00000000   # Output Data (GPIO Bank3, EMIO)  # writing 0 to EMIO GPIO 0     
  9. After 1000
    #De-assert reset (active high)
  10. mwr 0xFF0A004C 0x00000001   # Output Data (GPIO Bank3, EMIO)  # writing 1 to EMIO GPIO 0     
  11. Now download ELF file for the PS-PL application

This issue is expected to be fixed in the 2016.1 release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66183 Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues N/A N/A
AR# 66220
Date Created 12/11/2015
Last Updated 12/29/2015
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2015.4
IP
  • Zynq UltraScale+ MPSoC Processing System