We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66224

Zynq UltraScale+ MPSoC Processing System IP - Zynq UltraScale+ MPSoC wrapper throws syntax error when project is set to VHDL - for PS-only design


I have a design with Zynq UltraScale+ and the target language is set to VHDL,

I am receiving syntax errors such as "there are no ports in the wrapper entity" during wrapper creation.


To work around this issue, always Set the Target Language in Vivado to "Verilog".




This issue is expected to be fixed in the 2016.1 release. (Improved messaging and reporting to detect the error situation early in the cycle)

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66183 Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues N/A N/A
AR# 66224
Date 12/29/2015
Status Active
Type General Article
  • Zynq UltraScale+ MPSoC
  • Vivado Design Suite - 2015.4
  • Zynq UltraScale+ MPSoC Processing System
Page Bookmarked