I have a design with Zynq UltraScale+ and the target language is set to VHDL,
I am receiving syntax errors such as "there are no ports in the wrapper entity" during wrapper creation.
To work around this issue, always Set the Target Language in Vivado to "Verilog".
This issue is expected to be fixed in the 2016.1 release. (Improved messaging and reporting to detect the error situation early in the cycle)