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AR# 66227

Zynq UltraScale+ MPSoC Processing System IP - Use of Split clock with slave interface


Use of the "Use separate clock for RD/WR" feature in IPI when using connection automation might not work correctly .

There is no Xilinx IP which supports two clocks on a single interface. Our interconnect does not support this either. However, the PS architecture and AMBA specifications do have provision for this. 

The downside is that the connection automation connects the AXI interface as a regular AXI Interface and connects one of the two clocks. This can lead to incorrect systems being generated by novice users.


To work around this issue, disable "Use Separate Clock For RD/WR" in PCW.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66183 Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues N/A N/A
AR# 66227
Date 12/29/2015
Status Active
Type Known Issues
  • Zynq UltraScale+ MPSoC
  • Vivado Design Suite - 2015.4
  • Zynq UltraScale+ MPSoC Processing System
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