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AR# 66232

Vivado 2015.4 - Zynq Processing System - New S_AXI_GP0/GP1 AXI shim


Starting from 2015.3 onwards, there is a new shim which has been introduced with S_AXI_GP0/GP1 and can be seen in the processing_system7.ttcl file as below.

Location: $Install_Location\Vivado\2015.4\data\ip\xilinx\processing_system7_v5_5\ttcl

xlnx_axi_wrshim_unwrap #


xlnx_axi_wrshim_unwrap #


This answer record contains information on its usefulness and a work around if you do not plan to use it


This shim has been hooked to S_AXI_GP0/GP1 interfaces only and is not applied to the other PS-PL interfaces. The shim serves the following purpose:

  1. Primarily intended for PCIe Lockup Scenarios but it can be used for any AXI master interface, Write Data (wrData) and Write Command (wrCmd) channel. 
  2. It will align the issuing of the Write Command (wrCmd) with the 1st Write Data (wrData) beat, so it will not allow a Write Address (wrAddr) to propagate without the 1st Write Data (wrData) beat being present. This is a desirable flow from the AXI point of view.
  3. There are no negative side-effects when using this module.

If you are not planning to use it, you can follow the steps below as a work-around:
  1. Download the attached processing_system7.ttcl (this is from the 2015.2 release).
  2. Go to the folder $Install_Location\Vivado\2015.4\data\ip\xilinx\processing_system7_v5_5\ttcl and rename the existing processing_system7.ttcl file to processing_system7.backup file.
  3. Copy over the 2015.2 downloaded file to that location.
  4. Re-generate the Processing System IP in Vivado IP Integrator.
  5. No other changes are required at the PS-PL interface level.

For further details, please feel free to contact Xilinx Technical Support.


Associated Attachments

Name File Size File Type
processing_system7.ttcl 151 KB TTCL
AR# 66232
Date 01/05/2016
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2015.4
  • Processing System 7
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