We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66278

Zynq UltraScale+ MPSoc, Vivado 2015.4 - SDK/XSDB debugger unable to read/write PL peripherals: "PL AXI slave ports access is not allowed"


I have a simple MPSoC project with a BRAM in the PL. However, if I try do a memory read in XSDB (mrd), I get an error stating the following:

PL AXI slave ports access is not allowed

How can this be addressed?


Currently, the PL address ranges are not exported to the debugger as an allowable region to access.

The -force switch needs to be used to access the unknown range.

For example:

mrd -force 0x80000000

This issue is currently planned to be fixed starting in Vivado 2016.1.

AR# 66278
Date 12/21/2015
Status Active
Type General Article
  • Vivado Design Suite - 2015.4.1
Page Bookmarked