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AR# 66280

Vivado Synthesis - Port logic trimmed when SystemVerilog interface contains no port direction

Description

I am using an interface to define my module ports. However, after Synthesis, the underlying logic is trimmed:

interface flop_ifc;
   logic          clk;
   logic          rst;
   logic          pkt_req;
   logic          pkt_req_ack;
   logic          pkt_in_prog;
endinterface

module flop (
   flop_ifc     f
);

Solution

It is highly recommended to use modports in an interface when using Vivado Synthesis. Not doing so forces the synthesis tool to figure out the direction on each level and this does not always work correctly. 

To work around this issue, use a modport in the interface to determine direction as shown in the example below:


interface flop_ifc;
   logic          clk;
   logic          rst;
   logic          pkt_req;
   logic          pkt_req_ack;
   logic          pkt_in_prog;
   
   modport example (input clk, rst, pkt_req, pkt_in_prog, output pkt_req_ack);
endinterface

module flop (
   flop_ifc.example     f
);

AR# 66280
Date Created 12/18/2015
Last Updated 09/22/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite
  • Vivado Design Suite - 2015.4