Exporting simulation results in the following elaboration error:
The problem is that the compilation scripts generated by the export simulation will be wrong for certain IP the first time they are generated.
The IP impacted seems to be scoped to non-block design based hierarchical IP with more than two levels of IP nesting (for example, AXI DMA) when global synthesis is on.
Export simulation scripts for AXI DMA (and any non-scoped BD based HIP with 3 levels of instantiation) are incorrect when that IP is first generated and set to global synthesis.
To work around the issue, reset and regenerate (slow), or close and reopen the project then rerun the export simulation Tcl command.
This issue is fixed in Vivado 2015.4.