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AR# 66281

2015.3 Vivado IP Flows - Exported simulation script fails for AXI bridge for PCIe Express and PCIe DMA subsystem

Description

Exporting simulation results in the following elaboration error:

Starting static elaboration
ERROR: [VRFC 10-2063] Module <axi_pcie3_0_pcie3_ip_gt> not found while processing module instance <axi_pcie3_0_pcie3_ip_gt_i> [<My_proj>/ip_user_files/ip/axi_pcie3_0/ip_2/source/axi_pcie3_0_pcie3_ip_gtwizard_top.v:465]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
ERROR: Please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/axi_pcie3_0/xsimk" does not exist
[usr1@server xsim]$
vlog.prj has following missing :
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_bit_synchronizer.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_gthe3_cpll_cal.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_gthe3_cpll_cal_freq_counter.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_gtwiz_buffbypass_rx.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_gtwiz_buffbypass_tx.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_gtwiz_reset.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_gtwiz_userclk_rx.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_gtwiz_userclk_tx.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_gtwiz_userdata_rx.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_gtwiz_userdata_tx.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ipstatic/gtwizard_ultrascale_v1_5_3/hdl/verilog/gtwizard_ultrascale_v1_5_reset_synchronizer.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"
verilog gtwizard_ultrascale_v1_5_3 "./../../../ip/axi_pcie3_0/ip_2/ip_0/sim/gtwizard_ultrascale_v1_5_gthe3_channel.v" --include "./../../../ip/axi_pcie3_0/axi_pcie3_v2_0_0/hdl/verilog" --include "./../../../ipstatic/axi_pcie3_v2_0_0/hdl/verilog"

Solution

The problem is that the compilation scripts generated by the export simulation will be wrong for certain IP the first time they are generated. 

The IP impacted seems to be scoped to non-block design based hierarchical IP with more than two levels of IP nesting (for example, AXI DMA) when global synthesis is on.

Export simulation scripts for AXI DMA (and any non-scoped BD based HIP with 3 levels of instantiation) are incorrect when that IP is first generated and set to global synthesis.

To work around the issue, reset and regenerate (slow), or close and reopen the project then rerun the export simulation Tcl command.

This issue is fixed in Vivado 2015.4.

AR# 66281
Date Created 12/18/2015
Last Updated 12/22/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2015.3