We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66291

2015.4 Vivado IP Flows - AXI 10g Ethernet Example Design created from IPI Axi 10g Ethernet block fails in OOC generation with ERROR: [Synth 8-439] module 'bd_0_ten_gig_eth_pcs_pma_0' not found


I am unable to simulate an AXI 10 Gig Ethernet IP example design.

Generating the simulation models gives the following error.

CRITICAL WARNING: [exportsim-Tcl-45] The 'ten_gig_eth_pcs_pma_0' IP have not generated output products yet or have subsequently been updated, making the current output products out-of-date. It is strongly recommended that this IP be re-generated and then this script run again to get a complete output. To generate the output products please see 'generate_target' Tcl command. Status - (Not Generated) IP NAME = ten_gig_eth_pcs_pma_0

Attempting to simulate results in the following error:

ERROR: [VRFC 10-2063] Module <bd_0_ten_gig_eth_pcs_pma_0> not found while processing module instance <ten_gig_eth_pcs_pma> [/my_proj/axi_10g_ethernet_ku_example.srcs/sources_1/ip/axi_10g_ethernet_ku/bd_0/hdl/bd_0.v:396]

Running the same simulation script procedure in Vivado 2015.3 does not produce an error.


The export_simulation command, which is called from the export_ip_user_files command is expecting the simulation targets to be generated for the IP.

However, the IP does not have their simulation targets generated.
The ten_gig_eth_pcs_pma is failing during generation when the -quiet switch is used.
This does not affect generation in the GUI, but does in the example script. 

The IP uses the -quiet switch when generating the targets and the IP is failing during generation, leaving the IP in an incorrect state.
The project thinks the IP is fully generated when it is not.

When the -quiet option is used in the script, only the instantiation_template is processed.
The synthesis and simulation targets are not generated.
The script is failing in the synthesis wrapper output product. Because the quiet switch is on, this is not reported. 

Specifically, it is failing when evaluating the TTCL file: ttcl/ten_gig_eth_pcs_pma_wrapper_vhd.ttcl.

To work around this issue, remove the -quiet option from the script before running and all three targets are generated as expected.

This issue is scheduled to be fixed in Vivado 2016.1

AR# 66291
Date 01/04/2016
Status Active
Type Known Issues
  • Vivado Design Suite - 2015.4
Page Bookmarked