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When using an AXI interface with 32 or 64-bit width (or 128-bits for M_AXI_HP0_LPD), the data is not arranged correctly, causing data corruption.
How do I resolve this?
Although the IP Integrator interface section is parameterized correctly, the PS registers which control the width are not updated in psu_init.tcl/.c, which is used by the debugger and FSBL.
To work around this issue, manually access the register and configure the AXI width before allowing AXI interface.
There are two issues in the current version of PCW:
To work around this issue, manually add the AXI width register setting to psu_ps_pl_isolation_removal_data() proc in psu_init, as these settings are used only when there is logic in the PL.
Nothing needs to done for the AFI module reset because it has been released from reset prior to this step.
The relevant registers to be modified are:
AXI Interface | Register Name | Address | Bits |
---|---|---|---|
M_AXI_HPM0_FPD | FPD_SLCR.axi_fs.dw_ss0_sel | 0xFD615000 | 9:8 |
M_AXI_HPM1_FPD | FPD_SLCR.axi_fs.dw_ss1_sel | 0xFD615000 | 11:10 |
M_AXI_HPM0_LPD | LPD_SLCR.axi_fs.dw_ss2_sel | 0xFF419000 | 9:8 |
S_AXI_HPC0_FPD | AFIFM0.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM0.AFIFM_WRCTRL.FABRIC_WIDTH | 0xFD360000 and 0xFD360014 | 1:0 |
S_AXI_HPC1_FPD | AFIFM1.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM1.AFIFM_WRCTRL.FABRIC_WIDTH | 0xFD370000 and 0xFD370014 | 1:0 |
S_AXI_HP0_FPD | AFIFM2.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM2.AFIFM_WRCTRL.FABRIC_WIDTH | 0xFD380000 and 0xFD380014 | 1:0 |
S_AXI_HP1_FPD | AFIFM3.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM3.AFIFM_WRCTRL.FABRIC_WIDTH | 0xFD390000 and 0xFD390014 | 1:0 |
S_AXI_HP2_FPD | AFIFM4.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM4.AFIFM_WRCTRL.FABRIC_WIDTH | 0xFD3A0000 and 0xFD3A0014 | 1:0 |
S_AXI_HP3_FPD | AFIFM5.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM5.AFIFM_WRCTRL.FABRIC_WIDTH | 0xFD3B0000 and 0xFD3B0014 | 1:0 |
S_AXI_LPD | AFIFM6.AFIFM_RDCTRL.FABRIC_WIDTH and AFIFM6.AFIFM_WRCTRL.FABRIC_WIDTH | 0xFF9B0000 and 0xFF9B0014 | 1:0 |
Register Values:
FPD_SLCR registers:
AXIFM registers:
In Vivado 2016.3:
In Vivado 2016.4:
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
66183 | Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues | N/A | N/A |
AR# 66295 | |
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Date | 12/11/2017 |
Status | Active |
Type | General Article |
Devices |
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Tools |
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IP |
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