Description

When using an AXI interface with 32 or 64-bit width (or 128-bits for M_AXI_HP0_LPD), the data is not arranged correctly, causing data corruption.

How do I resolve this?

Solution

Although the IP Integrator interface section is parameterized correctly, the PS registers which control the width are not updated in psu_init.tcl/.c, which is used by the debugger and FSBL.

To work around this issue, manually access the register and configure the AXI width before allowing AXI interface.

There are two issues in the current version of PCW:

1. PS-PL AXI interface width settings are not correctly reflecting in psu_init. RDCTRL and WRCTRL registers for read and write channels should be written as per the AFI width configuration in PCW.
2. The register writes for PS-PL AXI interface related settings are done before the AFI module is released from reset, so these settings have no effect. These settings should be done after AFI is released from reset.

To work around this issue, manually add the AXI width register setting to psu_ps_pl_isolation_removal_data() proc in psu_init, as these settings are used only when there is logic in the PL. 

Nothing needs to done for the AFI module reset because it has been released from reset prior to this step.

The relevant registers to be modified are:

Register Values:

FPD_SLCR registers:

• 2'b00 : 32-bit enabled
• 2'b01 : 64-bit enabled
• 2'b10 : 128-bit enabled
• 2'b11 : Reserved

AXIFM registers:

• 2'b11 : Reserved
• 2'b10 : 32-bit Fabric
• 2'b01 : 64-bit enabled
• 2'b00 : 128-bit enabled

In Vivado 2016.3:

• JTAG Tcl flow was resolved, but FSBL flow still existed, see (Xilinx Answer 68166)

In Vivado 2016.4:

• This issue is addressed if the bitstream is loaded from FSBL.
• If the bitstream is loaded from u-boot or Linux the issue is still present.

• All known issues resolved.
  

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