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AR# 66340

Using XSDB to access the PL from the RPU

Description

(Xilinx Answer 66219) covers taking the A53-0 out of reset, and interacting with the design when the XSDB target is set to A53-0. 

In order to use the R5 as an XSDB target and access the PL, the R5 and RPU AMBA need to be taken out of reset.

These instructions also show how to use XSDB to interact with TCM from both the R5 and A53.

Solution

Execute the following commands in XSDB in order to manually initialize the RPU:

  connect
  targets -set -filter {name =~ "PSU"};
  # Informational. Not necessary just to access the PL from R5 in XSDB
  #   Set R5 reset vectors low (to TCM) and make sure CPUHALT is set to R5
  #   will not fetch upon exiting reset
  mwr 0xFF9A0100 0x00000001;  #RPU:RPU_0_CFG: [2]-VINITHI  [0]-nCPUHALT

  # Informational. Not necessary just to access the PL from R5 in XSDB
  #   Set R5 split mode
  mask_write 0xFF9A0050 0x00000008 0x00000008;   #RPU:RPU_GLBL_CNTL [3]-SLSPLIT
 
  #Take R5-0 and RPU AMBA out of reset
  mask_write 0xFF5E023C 0x00000005 0x00000000;   #CRL_APB:RST_LPD_TOP: [3]-ocm_reset, [2]-rpu_amba_reset, [1]-rpu_r51_reset, [0]-rpu_r50_reset


The following commands can be used to write to an axi_gpio that is located in PL at 0x80010000:

  #Write LEDs from R5-0 on LPD PS-PL port
  targets -set -filter {name =~ "Cortex-R5 #0"};
  mwr -force 0x80010000 0x5

The following commands can be used to write to TCM from the R5:

  #See that TCM is accessible
  # Couldn't disable ECC so write first then read
  targets -set -filter {name =~ "Cortex-R5 #0"};
  mwr 0x00000000 0xface00ff
  puts "TCM   Expect:0xFACE00FF";
  puts "R5-0  Read  :[format 0x%4.4X [mrd -value 0x00000000]]";

The following commands can be used to read TCM from the A53

  #Read TCM from A53-0
  targets -set -filter {name =~ "Cortex-A53 #0"};
  puts "A53-0 Read  :[format 0x%4.4X [mrd -value 0xffe00000]]";

AR# 66340
Date Created 01/05/2016
Last Updated 01/13/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2015.4
Boards & Kits
  • Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit